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fixed perf counters
This commit is contained in:
Pasquale Davide Schiavone
parent
ef744a9174
commit
e97d18e829
6 changed files with 36 additions and 52 deletions
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@ -74,7 +74,6 @@ module zeroriscy_controller
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input logic branch_taken_ex_i, // branch taken signal
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input logic branch_set_i, // branch taken set signal
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input logic jump_set_i, // jump taken set signal
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input logic jump_in_id_i, // jump is being calculated in ALU
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input logic instr_multicyle_i, // multicycle instructions active
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@ -114,17 +113,11 @@ module zeroriscy_controller
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output logic halt_if_o,
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output logic halt_id_o,
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input logic jump_stall_i,
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input logic load_stall_i,
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input logic branch_stall_i,
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input logic id_ready_i, // ID stage is ready
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_jr_stall_o, // stall due to jump instruction
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output logic perf_br_stall_o, // stall due to branch instruction
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output logic perf_ld_stall_o // stall due to load instruction
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output logic perf_tbranch_o // we are executing a taken branch instruction
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);
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// FSM state encoding
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@ -203,6 +196,9 @@ module zeroriscy_controller
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// - Debuger requests halt
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dbg_trap_o = 1'b0;
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perf_tbranch_o = 1'b0;
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perf_jump_o = 1'b0;
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unique case (ctrl_fsm_cs)
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// We were just reset, wait for fetch_enable
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RESET:
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@ -300,6 +296,7 @@ module zeroriscy_controller
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branch_set_i: begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_tbranch_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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if (dbg_req_i)
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ctrl_fsm_ns = DBG_SIGNAL;
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@ -307,6 +304,7 @@ module zeroriscy_controller
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jump_set_i: begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_jump_o = 1'b1;
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dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
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if (dbg_req_i)
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ctrl_fsm_ns = DBG_SIGNAL;
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@ -531,12 +529,6 @@ module zeroriscy_controller
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end
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end
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// Performance Counters
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assign perf_jump_o = jump_in_id_i;
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assign perf_jr_stall_o = jump_stall_i;
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assign perf_br_stall_o = branch_stall_i;
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assign perf_ld_stall_o = load_stall_i;
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//----------------------------------------------------------------------------
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// Assertions
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@ -221,8 +221,8 @@ module zeroriscy_core
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// Performance Counters
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logic perf_imiss;
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logic perf_jump;
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logic perf_jr_stall;
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logic perf_ld_stall;
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logic perf_branch;
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logic perf_tbranch;
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//core busy signals
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logic core_ctrl_firstfetch, core_busy_int, core_busy_q;
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@ -328,6 +328,7 @@ module zeroriscy_core
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// pipeline stalls
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.halt_if_i ( halt_if ),
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.id_ready_i ( id_ready ),
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.if_valid_o ( if_valid ),
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.if_busy_o ( if_busy ),
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.perf_imiss_o ( perf_imiss )
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@ -455,8 +456,9 @@ module zeroriscy_core
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// Performance Counters
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.perf_jump_o ( perf_jump ),
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.perf_jr_stall_o ( perf_jr_stall ),
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.perf_ld_stall_o ( perf_ld_stall )
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.perf_branch_o ( perf_branch ),
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.perf_tbranch_o ( perf_tbranch )
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);
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@ -593,6 +595,7 @@ module zeroriscy_core
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// performance counter related signals
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.if_valid_i ( if_valid ),
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.id_valid_i ( id_valid ),
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.is_compressed_i ( is_compressed_id ),
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.is_decoding_i ( is_decoding ),
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@ -600,11 +603,8 @@ module zeroriscy_core
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.imiss_i ( perf_imiss ),
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.pc_set_i ( pc_set ),
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.jump_i ( perf_jump ),
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.branch_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.ld_stall_i ( perf_ld_stall ),
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.jr_stall_i ( perf_jr_stall ),
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.branch_i ( perf_branch ),
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.branch_taken_i ( perf_tbranch ),
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.mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ),
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.mem_store_i ( data_req_o & data_gnt_i & data_we_o ),
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@ -75,6 +75,7 @@ module zeroriscy_cs_registers
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// Performance Counters
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input logic if_valid_i, // IF stage gives a new instruction
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input logic id_valid_i, // ID stage is done
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input logic is_compressed_i, // compressed instruction in ID
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input logic is_decoding_i, // controller is in DECODE state
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@ -84,12 +85,8 @@ module zeroriscy_cs_registers
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input logic jump_i, // jump instruction seen (j, jr, jal, jalr)
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input logic branch_i, // branch instruction seen (bf, bnf)
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input logic branch_taken_i, // branch was taken
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input logic ld_stall_i, // load use hazard
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input logic jr_stall_i, // jump register use hazard
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input logic mem_load_i, // load from memory in this cycle
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input logic mem_store_i, // store to memory in this cycle
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input logic [N_EXT_CNT-1:0] ext_counters_i
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);
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@ -314,14 +311,16 @@ module zeroriscy_cs_registers
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/////////////////////////////////////////////////////////////////
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assign PCCR_in[0] = 1'b1; // cycle counter
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assign PCCR_in[1] = id_valid_i & is_decoding_i; // instruction counter
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assign PCCR_in[1] = if_valid_i; // instruction counter
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assign PCCR_in[2] = 1'b0; // Reserved
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assign PCCR_in[3] = 1'b0; // Reserved
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assign PCCR_in[4] = imiss_i & (~pc_set_i); // cycles waiting for instruction fetches, excluding jumps and branches
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assign PCCR_in[5] = mem_load_i; // nr of loads
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assign PCCR_in[6] = mem_store_i; // nr of stores
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assign PCCR_in[7] = jump_i & id_valid_q; // nr of jumps (unconditional)
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assign PCCR_in[8] = branch_i & id_valid_q; // nr of branches (conditional)
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assign PCCR_in[9] = branch_i & branch_taken_i & id_valid_q; // nr of taken branches (conditional)
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assign PCCR_in[10] = id_valid_i & is_decoding_i & is_compressed_i; // compressed instruction counter
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assign PCCR_in[7] = jump_i; // nr of jumps (unconditional)
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assign PCCR_in[8] = branch_i; // nr of branches (conditional)
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assign PCCR_in[9] = branch_taken_i; // nr of taken branches (conditional)
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assign PCCR_in[10] = id_valid_i & is_decoding_i & is_compressed_i; // compressed instruction counter
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// assign external performance counters
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generate
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@ -347,7 +346,7 @@ module zeroriscy_cs_registers
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unique case (csr_addr_i)
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12'h7A0: begin
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is_pcer = 1'b1;
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perf_rdata[N_PERF_COUNTERS-1:0] = PCER_q;
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perf_rdata[15:0] = PCER_q;
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end
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12'h7A1: begin
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is_pcmr = 1'b1;
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@ -68,7 +68,7 @@ module zeroriscy_ex_block
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output logic ex_ready_o // EX stage gets new data
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);
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localparam MULT_TYPE = 0; //0 is SLOW
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localparam MULT_TYPE = 1; //0 is SLOW
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logic [31:0] alu_result, multdiv_result;
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@ -150,8 +150,8 @@ module zeroriscy_id_stage
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction
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output logic perf_jr_stall_o, // jump-register-hazard
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output logic perf_ld_stall_o // load-use-hazard
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output logic perf_branch_o, // we are executing a branch instruction
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output logic perf_tbranch_o // we are executing a taken branch instruction
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);
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logic [31:0] instr;
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@ -552,7 +552,6 @@ module zeroriscy_id_stage
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.branch_taken_ex_i ( branch_taken_ex ),
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.branch_set_i ( branch_set_q ),
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.jump_set_i ( jump_set ),
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.jump_in_id_i ( jump_in_id ),
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.instr_multicyle_i ( instr_multicyle ),
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@ -589,17 +588,11 @@ module zeroriscy_id_stage
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.halt_if_o ( halt_if_o ),
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.halt_id_o ( halt_id ),
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.jump_stall_i ( jump_stall ),
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.branch_stall_i ( branch_stall ),
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.load_stall_i ( load_stall ),
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.id_ready_i ( id_ready_o ),
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// Performance Counters
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.perf_jump_o ( perf_jump_o ),
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.perf_jr_stall_o ( perf_jr_stall_o ),
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.perf_br_stall_o ( ),
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.perf_ld_stall_o ( perf_ld_stall_o )
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.perf_tbranch_o ( perf_tbranch_o )
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);
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////////////////////////////////////////////////////////////////////////
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@ -701,6 +694,7 @@ module zeroriscy_id_stage
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branch_mux_dec = 1'b0;
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jump_set = 1'b0;
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jump_mux_dec = 1'b0;
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perf_branch_o = 1'b0;
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unique case (id_wb_fsm_cs)
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@ -722,6 +716,7 @@ module zeroriscy_id_stage
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branch_stall = branch_decision_i;
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instr_multicyle = branch_decision_i;
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branch_set_n = branch_decision_i;
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perf_branch_o = 1'b1;
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end
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multdiv_int_en: begin
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//MUL or DIV operation
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@ -59,17 +59,15 @@ module zeroriscy_if_stage
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input logic [2:0] pc_mux_i, // sel for pc multiplexer
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input logic [1:0] exc_pc_mux_i, // selects ISR address
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input logic [4:0] exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines
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// jump and branch target and decision
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// jump and branch target and decision
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input logic [31:0] jump_target_ex_i, // jump target address
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// from hwloop controller
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// from debug unit
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input logic [31:0] dbg_jump_addr_i,
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// pipeline stall
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input logic halt_if_i,
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input logic id_ready_i,
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output logic if_valid_o,
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// misc signals
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output logic if_busy_o, // is the IF stage busy fetching instructions?
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output logic perf_imiss_o // Instruction Fetch Miss
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@ -79,7 +77,7 @@ module zeroriscy_if_stage
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enum logic[0:0] {WAIT, IDLE } offset_fsm_cs, offset_fsm_ns;
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logic valid;
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logic if_ready, if_valid;
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logic if_ready;
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// prefetch buffer related signals
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logic prefetch_busy;
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logic branch_req;
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@ -186,7 +184,7 @@ module zeroriscy_if_stage
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if (fetch_valid) begin
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid) begin
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if (req_i && if_valid_o) begin
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fetch_ready = 1'b1;
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offset_fsm_ns = WAIT;
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end
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@ -250,7 +248,7 @@ module zeroriscy_if_stage
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else
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begin
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if (if_valid)
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if (if_valid_o)
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begin
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instr_valid_id_o <= 1'b1;
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instr_rdata_id_o <= instr_decompressed;
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@ -266,7 +264,7 @@ module zeroriscy_if_stage
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assign if_ready = valid & id_ready_i;
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assign if_valid = (~halt_if_i) & if_ready;
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assign if_valid_o = (~halt_if_i) & if_ready;
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//----------------------------------------------------------------------------
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// Assertions
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