Add handling for NO_JUMP_ADDER in prefetcher

include/riscv_config.sv

@@ -113,6 +113,16 @@
 // will split ALU Adder in half and use two cycles to add operands
 `define SPLITTED_ADDER
 
+
+`ifdef SMALL_IF
+`ifndef JUMP_IN_ID
+// CONFIG: NO_JUMP_ADDER
+// will use ALU adder to calculate target and return address from prefetcher
+`define NO_JUMP_ADDER
+
+`endif
+`endif
+
 `endif
 `endif
 `endif

prefetch_buffer_only_aligned.sv

@@ -74,9 +74,7 @@ module riscv_prefetch_buffer_only_aligned
 
   assign busy_o = (CS != IDLE) || instr_req_o;
   assign addr_is_misaligned = (fetch_addr_Q[1] == 1'b1); // Check if address is misaligned
-
   assign instr_is_in_regs = (fetch_valid_Q && addr_is_misaligned);
-
   assign instr_mux = fetch_valid_Q ? fetch_rdata_Q : instr_rdata_i;
   assign fetch_rdata_n = instr_mux;
 

prefetch_buffer_small.sv

@@ -213,6 +213,12 @@ module riscv_prefetch_buffer_small
       WAIT_GNT: begin
         instr_req_o = 1'b1;
         instr_addr_o = {fetch_addr_Q[31:2], 2'b00};
+
+        // CONFIG_REGION: NO_JUMP_ADDER
+        `ifdef NO_JUMP_ADDER
+        if (is_second_fetch_n)
+          addr_o = last_fetch_addr_Q;
+        `endif
         
         if (~branch_i) begin
           if (instr_gnt_i)
@@ -242,6 +248,12 @@ module riscv_prefetch_buffer_small
 
 
       WAIT_RVALID: begin
+        // CONFIG_REGION: NO_JUMP_ADDER
+        `ifdef NO_JUMP_ADDER
+        if (is_second_fetch_n)
+          addr_o = last_fetch_addr_Q;
+        `endif
+
         if (~branch_i) begin
           
           NS = WAIT_RVALID;