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update tracer and elw

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This commit is contained in:
Pasquale Davide Schiavone 2017-01-27 16:16:13 +01:00
parent c24081a1b8
commit 46fe850b05
4 changed files with 16 additions and 9 deletions
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1
controller.sv
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@ -247,6 +247,7 @@ module littleriscv_controller
DECODE:
begin
//TODO: define interrupt during sw/lw
is_decoding_o = 1'b0;
// decode and execute instructions only if the current conditional

2
id_stage.sv
View file

@ -664,7 +664,7 @@ module littleriscv_id_stage
data_req_ex_o = data_req_id;
data_reg_offset_ex_o = data_reg_offset_id;
data_load_event_ex_o = ((data_req_id & (~halt_id) & wb_ready_i) ? data_load_event_id : 1'b0);
data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0);
branch_in_ex_o = (jump_in_dec == BRANCH_COND);
end

9
littleriscv_core.sv
View file

@ -687,7 +687,7 @@ module littleriscv_core
.ex_reg_addr ( id_stage_i.regfile_waddr_mux ),
.ex_reg_we ( id_stage_i.regfile_we_mux ),
.ex_reg_wdata ( id_stage_i.regfile_wdata_mux ),
.data_valid_lsu ( data_valid_lsu ),
.ex_data_addr ( data_addr_o ),
.ex_data_req ( data_req_o ),
.ex_data_gnt ( data_gnt_i ),
@ -697,9 +697,9 @@ module littleriscv_core
.wb_bypass ( branch_in_ex_o ),
.wb_valid ( data_valid_lsu ),
.wb_reg_addr ( ),
.wb_reg_we ( ),
.wb_valid ( ),
.wb_reg_addr ( ),
.wb_reg_we ( ),
.wb_reg_wdata ( regfile_wdata_lsu ),
.imm_u_type ( id_stage_i.imm_u_type ),
@ -750,7 +750,6 @@ module littleriscv_core
.ex_reg_we ( id_stage_i.registers_i.we_a_i ),
.ex_reg_wdata ( id_stage_i.registers_i.wdata_b_i ),
.data_valid_lsu ( data_valid_lsu )
.ex_data_addr ( data_addr_o ),
.ex_data_req ( data_req_o ),
.ex_data_gnt ( data_gnt_i ),

13
riscv_tracer.sv
View file

@ -712,7 +712,14 @@ module littleriscv_tracer
trace.regs_write[i].value = ex_reg_wdata;
end
// look for data accesses and log them
if (ex_data_req && ex_data_gnt) begin
if (ex_data_req) begin
if(~ex_data_gnt) begin
//we wait until the the gnt comes
do @(negedge clk);
while (!ex_data_gnt);
end
mem_acc.addr = ex_data_addr;
mem_acc.we = ex_data_we;
@ -720,15 +727,15 @@ module littleriscv_tracer
mem_acc.wdata = ex_data_wdata;
else
mem_acc.wdata = 'x;
trace.mem_access.push_back(mem_acc);
//we wait until the the data instruction ends
do @(negedge clk);
while (!data_valid_lsu);
if (~mem_acc.we)
//load operations
foreach(trace.regs_write[i])
trace.regs_write[i].value = wb_reg_wdata;
trace.mem_access.push_back(mem_acc);
end
trace.printInstrTrace();