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Update google_riscv-dv to google/riscv-dv@9c2b007

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Update code from upstream repository https://github.com/google/riscv-
dv to revision 9c2b007eea5baed25dc9b4c3181c2f328f98a2af

* [pmp] Add knob to suppress PMP setup code (Greg Chadwick)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This commit is contained in:
Greg Chadwick 2022-09-01 10:14:36 +01:00 • committed by Greg Chadwick
parent 056cb44ff7
commit 494438dc4e
3 changed files with 24 additions and 3 deletions
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2
vendor/google_riscv-dv.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 68e3bcac7293ac79067f0d8196bb973bd7c889cf
rev: 9c2b007eea5baed25dc9b4c3181c2f328f98a2af
}
}

11
vendor/google_riscv-dv/src/riscv_asm_program_gen.sv vendored
View file

@ -829,8 +829,15 @@ class riscv_asm_program_gen extends uvm_object;
virtual function void setup_pmp(int hart);
string instr[$];
if (riscv_instr_pkg::support_pmp) begin
cfg.pmp_cfg.setup_pmp();
cfg.pmp_cfg.gen_pmp_instr('{cfg.scratch_reg, cfg.gpr[0]}, instr);
if(cfg.pmp_cfg.suppress_pmp_setup) begin
// When PMP setup is suppressed generate a configuration that gives unrestricted access to
// all memory for both M and U mode
cfg.pmp_cfg.gen_pmp_enable_all(cfg.scratch_reg, instr);
end else begin
cfg.pmp_cfg.setup_pmp();
cfg.pmp_cfg.gen_pmp_instr('{cfg.scratch_reg, cfg.gpr[0]}, instr);
end
gen_section(get_label("pmp_setup", hart), instr);
end
endfunction

14
vendor/google_riscv-dv/src/riscv_pmp_cfg.sv vendored
View file

@ -39,6 +39,10 @@ class riscv_pmp_cfg extends uvm_object;
// allowing all access restrictions to be enforced.
bit enable_pmp_exception_handler = 1'b1;
// Don't generate the usual PMP setup section, instead generate a setup that provides a single
// region allowing full access to all of memory from both U mode and M mode.
bit suppress_pmp_setup = 0;
// Setting this bit to 1'b1 enables generation of the directed stream of instructions to test
// write accesses to all supported pmpaddr[i] CSRs.
bit enable_write_pmp_csr;
@ -141,6 +145,7 @@ class riscv_pmp_cfg extends uvm_object;
get_int_arg_value("+pmp_granularity=", pmp_granularity);
get_bool_arg_value("+pmp_randomize=", pmp_randomize);
get_bool_arg_value("+pmp_allow_addr_overlap=", pmp_allow_addr_overlap);
get_bool_arg_value("+suppress_pmp_setup=", suppress_pmp_setup);
get_bool_arg_value("+enable_write_pmp_csr=", enable_write_pmp_csr);
get_hex_arg_value("+pmp_max_offset=", pmp_max_offset);
`uvm_info(`gfn, $sformatf("pmp max offset: 0x%0x", pmp_max_offset), UVM_LOW)
@ -307,6 +312,15 @@ class riscv_pmp_cfg extends uvm_object;
`uvm_info(`gfn, "Placeholder function, need to implement", UVM_LOW)
endfunction
// Generates code to setup a single PMP region allowing full access to all memory
function void gen_pmp_enable_all(riscv_reg_t scratch_reg, ref string instr[$]);
// Setup region 0 to NAPOT covering the whole 32-bit address space, with RWX permissions and no
// lock.
instr.push_back($sformatf("li x%0d, 0x1fffffff", scratch_reg));
instr.push_back($sformatf("csrw 0x%0x, x%0d", PMPADDR0, scratch_reg));
instr.push_back($sformatf("csrw 0x%0x, 0x1f", PMPCFG0));
endfunction
// This function parses the pmp_cfg[] array to generate the actual instructions to set up
// the PMP CSR registers.
// Since either 4 (in rv32) or 8 (in rv64) PMP configuration registers fit into one physical