Update lowrisc_ip to lowRISC/opentitan@3a672eb36

This commit also adds memory manipulation package in ibex repository.

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
3a672eb36aee5942d0912a15d15055b1d21c33d6

* [mubi] Fix path in auto-gen header (Rupert Swarbrick)
* [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr
  (Rupert Swarbrick)
* [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal)
* [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan
  Shapira)
* [dv] Add external hjson path support in ralgen (Srikrishna Iyer)
* [dv] Add sub RAL block creation knobs (Srikrishna Iyer)
* [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen)
* [dv/alert_handler] Randomize mubi input (Cindy Chen)
* [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen)
* [ci] Fix CI failure (Weicai Yang)
* [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai
  Yang)
* [aes] Add gtech synthesis setup (Michael Schaffner)
* [mubi] Enhance mubi_sync with stability check (Timothy Chen)
* [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert
  Swarbrick)
* [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang)
* [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick)
* [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen)
* [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert
  Swarbrick)
* [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick)
* [prim] Add option to not clear the packer FIFO upon read (Pirmin
  Vogel)
* [dv] Change intg_err test from V3 to V2S (Weicai Yang)
* [util] Delete generate_prim_mubi.py (Rupert Swarbrick)
* [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert
  Swarbrick)
* [fpv] Fix some assumptions in prim_count (Cindy Chen)
* [prim] quick path to prim_count assertion (Timothy Chen)
* [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal)
* [prim] Add xoshiro256pp primitive. (Vladimir Rozic)
* [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen)
* [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert
  Swarbrick)
* [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick)
* [dv/prim_alert_receiver] Fix assertion that consumes large mem
  (Cindy Chen)
* [prim] Remove extra semicolon (Weicai Yang)
* [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer)
* [top, all] update connects for mubi (Timothy Chen)
* [flash_ctrl] Add plain text integrity in flash (Timothy Chen)
* [prim] Add time-out functionality to prim_clock_meas (Timothy Chen)
* [prim] Fix DC sythesis error (Weicai Yang)
* [fpv] Fix regression failures (Cindy Chen)
* [dv/ralgen] Update `dv_base_names` input from a string to a list
  (Cindy Chen)
* [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen)
* [doc] Add D2S and V2S checklist items to all checklists (Michael
  Schaffner)
* [dv] Test security countermeasures (Weicai Yang)
* [dv] Fix ASSERT_INIT race condition (Weicai Yang)
* [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael
  Schaffner)
* [all] updated assert rtl ifdef (Timothy Chen)
* [dv] Update TL intg testplan (Weicai Yang)
* [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim)
* [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim)
* [dvsim] Modify resolve_branch to handle branch names with forward
  slash. (Todd Broch)
* [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner)
* [ralgen] Be more explicit which tool is called (Philipp Wagner)
* [prim] Tweak prim_sync_reqack_data assertion so it can be disabled
  (Rupert Swarbrick)
* [verible] Rename rule file (Philipp Wagner)
* [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen)
* [fpv] prim_counter_fpv (Cindy Chen)
* [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy
  Chen)
* [dv] Fix scb multi-ral (Weicai Yang)
* [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer)
* [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang)
* [dv/dsim] Remove dsim's system_lib from library path (Guillermo
  Maturana)
* [prim_packer] Resolve width mismatch (Philipp Wagner)
* [prim] Fix lint error in prim_util_memload (Philipp Wagner)
* [prim] Minor fix to make conn checks easy (Srikrishna Iyer)
* [fpv] prim_secded FPV testbench updates bind file naming (Cindy
  Chen)
* [dv_macros.svh] minor cleanup (Srikrishna Iyer)
* [dv,xcelium] minor cleanup (Srikrishna Iyer)
* [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen)
* [fpv] Update FPV file naming (Cindy Chen)
* [top] Convert to mubi usage in some areas (Timothy Chen)
* [entropy_src] mubi updates (Timothy Chen)
* [prim] Add test for mubi invalid (Timothy Chen)
* [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner)
* [dv] Fix shadow reg backdoor path and enable csr_reset sequence
  (Weicai Yang)
* [prim] Fix unused net (Timothy Chen)
* [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer)
* [prim] Anchor buffers around register flip flops (Timothy Chen)
* [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions
  (Michael Schaffner)
* [prim_mubi] Replace true/false_value() functions with parameter
  (Michael Schaffner)
* [dv/dsim] Get dsim to work at full chip (Guillermo Maturana)
* [prim] Fixes for prim_count (Timothy Chen)
* [top] Add various anchor points to modules (Timothy Chen)
* [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana)
* [reggen] Add mubi support into hjson (Timothy Chen)
* [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen)
* [dv/cdc] CDC simulation model (Udi Jonnalagadda)
* [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error
  (Michael Schaffner)
* [prim_clock_buf] Add lint waiver for unused parameter (Michael
  Schaffner)
* [dvsim] Correctly set self_dir for included Hjson files (Philipp
  Wagner)
* [util] Add tooling support for V2S milestone (Srikrishna Iyer)
* [prim_mubi] Add decoder module similar to prim_lc_dec (Michael
  Schaffner)
* [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner)
* [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner)
* [prim] Minor work-around for xcelium (Timothy Chen)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

vendor/lowrisc_ip/dv/tools/ralgen/README.md

@@ -15,10 +15,20 @@ The adjoining `ralgen.core` file registers the `ralgen` generator. The FuseSoC
 core file that 'calls' the generator adds it as a dependency. When calling the
 generator, the following parameters are set:
 * **name (mandatory)**: Name of the RAL package (typically, same is the IP).
-* **dv_base_prefix (optional)**: The prefix added to the base classes from
-  which the register classes are derived. Set this option to derive the register
-  classes not from the default `dv_base_reg`, but from user defined custom
-  class definitions.
+* **dv_base_names (optional)**: The base class names from which the register
+  classes are derived. Set this option to derive the register classes not from
+  the default `dv_base_reg`, but from user defined custom class definitions.
+  This argument follows the following format:
+  `--dv-base-names block:type:entity-name block:type:entity-name ...`.
+  `block`: can be any block names.
+  `type`: can be `block`, `reg`, `field`, `pkg`, `mem`, or use `all` to override
+  all types within the block.
+  `entity_name`: the name of the base class / package. If the `type` is set to `all`,
+  then this represents the prefix of the bass class / package. The suffixes
+  `_reg_block`, `_reg`, `_reg_field`, `_mem`, `_reg_pkg` are applied to infer the
+  actual base class / package names from which the generated DV classes will extend.
+  Note that we assume the fusesoc core file naming convention follows the package
+  name without the `_pkg` suffix.
 * **ip_hjson**: Path to the hjson specification written for an IP which includes
   the register descriptions. This needs to be a valid input for `reggen`.
 * **top_hjson**: Path to the hjson specification for a top level design. This
@@ -35,7 +45,9 @@ generate:
     parameters:
       name: <name>
       ip_hjson|top_hjson: <path-to-hjson-spec>
-      [dv_base_prefix: my_base]
+      [dv_base_names:
+        - block_1:type:entity_name_1
+        - block_2:type:entity_name_2]
 
 
 targets:
@@ -73,7 +85,7 @@ The generated core file adds **`lowrisc:dv:dv_base_reg`** as a dependency for
 the generated RAL package. This is required because our DV register block,
 register and field models are derived from the
 [DV library]({{< relref "hw/dv/sv/dv_lib/README.md" >}}) of classes. This
-ensures the right compilation order is maintained. If the `dv_base_prefix`
+ensures the right compilation order is maintained. If the `dv_base_names`
 argument is set, then it adds **`lowrisc:dv:my_base_reg`** as an extra
 dependency, where `my_base` is the value of the argument as shown in the
 example above. This core file and the associated sources are assumed to be

vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py

@@ -6,8 +6,10 @@ r"""FuseSoc generator for UVM RAL package created with either regtool or
 topgen tools.
 """
 import os
+import shlex
 import subprocess
 import sys
+from pathlib import Path
 
 import yaml
 
@@ -21,15 +23,6 @@ except ImportError:
 REPO_ROOT = "../../../.."
 
 
-# Given a root dir and partial path, this function returns the full path.
-def get_full_path(root_dir, partial_path):
-    full_path = os.path.abspath(os.path.join(root_dir, partial_path))
-    if not os.path.exists(full_path):
-        print("Error: path appears to be invalid: {}".format(full_path))
-        sys.exit(1)
-    return full_path
-
-
 def main():
     if len(sys.argv) != 2:
         print("ERROR: This script takes a single YAML file as input argument")
@@ -38,17 +31,17 @@ def main():
     gapi_filepath = sys.argv[1]
     gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
 
-    # This is just a wrapper around the reggen and topgen tools, which
-    # are referenced from proj_root area.
-    self_path = os.path.dirname(os.path.realpath(__file__))
-    util_path = os.path.abspath(os.path.join(self_path, REPO_ROOT, "util"))
+    # The reggen and topgen tools live in REPO_ROOT/util area.
+    util_path = Path(__file__).parent / REPO_ROOT / "util"
 
     # Retrieve the parameters from the yml.
-    root_dir = gapi['files_root']
+    root_dir = Path(gapi['files_root'])
     name = gapi['parameters'].get('name')
     ip_hjson = gapi['parameters'].get('ip_hjson')
     top_hjson = gapi['parameters'].get('top_hjson')
-    dv_base_prefix = gapi['parameters'].get('dv_base_prefix')
+    dv_base_names = gapi['parameters'].get('dv_base_names')
+    hjson_path = gapi['parameters'].get('hjson_path')
+
     if not name or (bool(ip_hjson) == bool(top_hjson)):
         print("Error: ralgen requires the \"name\" and exactly one of "
               "{\"ip_hjson\" and \"top_hjson\"} parameters to be set.")
@@ -56,24 +49,28 @@ def main():
 
     # Generate the RAL pkg.
     if ip_hjson:
-        ral_spec = get_full_path(root_dir, ip_hjson)
-        cmd = os.path.join(util_path, "regtool.py")
-        args = [cmd, "-s", "-t", ".", ral_spec]
+        ral_spec = root_dir / ip_hjson
+        cmd = util_path / "regtool.py"
+        args = [cmd, "-s", "-t", os.getcwd(), ral_spec]
     else:
-        ral_spec = get_full_path(root_dir, top_hjson)
-        cmd = os.path.join(util_path, "topgen.py")
-        args = [cmd, "-r", "-o", ".", "-t", ral_spec]
+        ral_spec = root_dir / top_hjson
+        cmd = util_path / "topgen.py"
+        args = [cmd, "-r", "-o", os.getcwd(), "-t", ral_spec]
+        if hjson_path:
+            args += ["--hjson-path", root_dir / hjson_path]
 
-    if dv_base_prefix and dv_base_prefix != "dv_base":
-        args.extend(["--dv-base-prefix", dv_base_prefix])
+    if dv_base_names:
+        args += ["--dv-base-names"] + dv_base_names
 
+    cmd_str = ' '.join([shlex.quote(str(arg)) for arg in args])
+    print(f"Calling tool in ralgen.py: {cmd_str}")
     try:
         subprocess.run(args, check=True)
     except subprocess.CalledProcessError as e:
-        print("Error: RAL pkg generation failed:\n{}".format(str(e)))
+        print(f"Error: RAL pkg generation failed:\n{e}")
         sys.exit(e.returncode)
-    print("RAL pkg for {} block written to {}"
-          .format(name, os.path.abspath('.')))
+
+    print(f"RAL pkg for {name} written to {Path.cwd()}.")
 
 
 if __name__ == '__main__':