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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
53b1732b19
This commit also adds memory manipulation package in ibex repository. Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a672eb36aee5942d0912a15d15055b1d21c33d6 * [mubi] Fix path in auto-gen header (Rupert Swarbrick) * [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr (Rupert Swarbrick) * [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal) * [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan Shapira) * [dv] Add external hjson path support in ralgen (Srikrishna Iyer) * [dv] Add sub RAL block creation knobs (Srikrishna Iyer) * [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen) * [dv/alert_handler] Randomize mubi input (Cindy Chen) * [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen) * [ci] Fix CI failure (Weicai Yang) * [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai Yang) * [aes] Add gtech synthesis setup (Michael Schaffner) * [mubi] Enhance mubi_sync with stability check (Timothy Chen) * [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert Swarbrick) * [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang) * [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick) * [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen) * [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert Swarbrick) * [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick) * [prim] Add option to not clear the packer FIFO upon read (Pirmin Vogel) * [dv] Change intg_err test from V3 to V2S (Weicai Yang) * [util] Delete generate_prim_mubi.py (Rupert Swarbrick) * [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert Swarbrick) * [fpv] Fix some assumptions in prim_count (Cindy Chen) * [prim] quick path to prim_count assertion (Timothy Chen) * [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal) * [prim] Add xoshiro256pp primitive. (Vladimir Rozic) * [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen) * [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert Swarbrick) * [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick) * [dv/prim_alert_receiver] Fix assertion that consumes large mem (Cindy Chen) * [prim] Remove extra semicolon (Weicai Yang) * [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer) * [top, all] update connects for mubi (Timothy Chen) * [flash_ctrl] Add plain text integrity in flash (Timothy Chen) * [prim] Add time-out functionality to prim_clock_meas (Timothy Chen) * [prim] Fix DC sythesis error (Weicai Yang) * [fpv] Fix regression failures (Cindy Chen) * [dv/ralgen] Update `dv_base_names` input from a string to a list (Cindy Chen) * [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen) * [doc] Add D2S and V2S checklist items to all checklists (Michael Schaffner) * [dv] Test security countermeasures (Weicai Yang) * [dv] Fix ASSERT_INIT race condition (Weicai Yang) * [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael Schaffner) * [all] updated assert rtl ifdef (Timothy Chen) * [dv] Update TL intg testplan (Weicai Yang) * [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim) * [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim) * [dvsim] Modify resolve_branch to handle branch names with forward slash. (Todd Broch) * [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner) * [ralgen] Be more explicit which tool is called (Philipp Wagner) * [prim] Tweak prim_sync_reqack_data assertion so it can be disabled (Rupert Swarbrick) * [verible] Rename rule file (Philipp Wagner) * [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen) * [fpv] prim_counter_fpv (Cindy Chen) * [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy Chen) * [dv] Fix scb multi-ral (Weicai Yang) * [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer) * [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang) * [dv/dsim] Remove dsim's system_lib from library path (Guillermo Maturana) * [prim_packer] Resolve width mismatch (Philipp Wagner) * [prim] Fix lint error in prim_util_memload (Philipp Wagner) * [prim] Minor fix to make conn checks easy (Srikrishna Iyer) * [fpv] prim_secded FPV testbench updates bind file naming (Cindy Chen) * [dv_macros.svh] minor cleanup (Srikrishna Iyer) * [dv,xcelium] minor cleanup (Srikrishna Iyer) * [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen) * [fpv] Update FPV file naming (Cindy Chen) * [top] Convert to mubi usage in some areas (Timothy Chen) * [entropy_src] mubi updates (Timothy Chen) * [prim] Add test for mubi invalid (Timothy Chen) * [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner) * [dv] Fix shadow reg backdoor path and enable csr_reset sequence (Weicai Yang) * [prim] Fix unused net (Timothy Chen) * [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer) * [prim] Anchor buffers around register flip flops (Timothy Chen) * [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions (Michael Schaffner) * [prim_mubi] Replace true/false_value() functions with parameter (Michael Schaffner) * [dv/dsim] Get dsim to work at full chip (Guillermo Maturana) * [prim] Fixes for prim_count (Timothy Chen) * [top] Add various anchor points to modules (Timothy Chen) * [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana) * [reggen] Add mubi support into hjson (Timothy Chen) * [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen) * [dv/cdc] CDC simulation model (Udi Jonnalagadda) * [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error (Michael Schaffner) * [prim_clock_buf] Add lint waiver for unused parameter (Michael Schaffner) * [dvsim] Correctly set self_dir for included Hjson files (Philipp Wagner) * [util] Add tooling support for V2S milestone (Srikrishna Iyer) * [prim_mubi] Add decoder module similar to prim_lc_dec (Michael Schaffner) * [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner) * [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner) * [prim] Minor work-around for xcelium (Timothy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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| .github | ||
| ci | ||
| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
| rtl | ||
| shared | ||
| syn | ||
| util | ||
| vendor | ||
| .clang-format | ||
| .gitignore | ||
| .svlint.toml | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_icache.core | ||
| ibex_multdiv.core | ||
| ibex_pkg.core | ||
| ibex_top.core | ||
| ibex_top_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
| src_files.yml | ||
| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
The block diagram below shows the small parametrization with a 2-stage pipeline.
Ibex was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It is under active development.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|---|
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.05 |
| Area - Yosys (kGE) | 17.44 | 26.06 | 35.64 | 58.74 |
| Area - Commercial (estimated kGE) | ~16 | ~24 | ~33 | ~54 |
| Verification status | Red | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform.
Note that different ISAs (use of B and C extensions) give the best results for different configurations.
See the Benchmarks README for more information.
The "maxperf-pmp-bmfull" configuration sets a
SpecBranchparameter inibex_core.sv; this helps timing but has a small negative performance impact. - Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
- v0.92 of the RISC-V Bit Manipulation Extension is supported. This is not ratified and there may be changes for the v1.0 ratified version. See Standards Compliance in the Ibex documentation for more information.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.