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[rtl] Switch to cluster_clock_gating

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This commit replaces the generic `prim_clock_gating` cell with the
`cluster_clock_gating` cell used in PULPissimo.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel 2020-02-21 13:23:02 +01:00
parent c69fc8b6f2
commit 57108c3184
2 changed files with 4 additions and 4 deletions
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2
rtl/ibex_core.sv
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@ -386,7 +386,7 @@ module ibex_core #(
// main clock gate of the core
// generates all clocks except the one for the debug unit which is
// independent
prim_clock_gating core_clock_gate_i (
cluster_clock_gating core_clock_gate_i (
.clk_i ( clk_i ),
.en_i ( clock_en ),
.test_en_i ( test_en_i ),

6
rtl/ibex_register_file_latch.sv
View file

@ -67,7 +67,7 @@ module ibex_register_file_latch #(
// WRITE //
///////////
// Global clock gating
prim_clock_gating cg_we_global (
cluster_clock_gating cg_we_global (
.clk_i ( clk_i ),
.en_i ( we_a_i ),
.test_en_i ( test_en_i ),
@ -99,7 +99,7 @@ module ibex_register_file_latch #(
// Individual clock gating (if integrated clock-gating cells are available)
for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
prim_clock_gating cg_i (
cluster_clock_gating cg_i (
.clk_i ( clk_int ),
.en_i ( waddr_onehot_a[x] ),
.test_en_i ( test_en_i ),
@ -129,7 +129,7 @@ module ibex_register_file_latch #(
assign we_r0_dummy = we_a_i & dummy_instr_id_i;
// R0 clock gate
prim_clock_gating cg_i (
cluster_clock_gating cg_i (
.clk_i ( clk_int ),
.en_i ( we_r0_dummy ),
.test_en_i ( test_en_i ),