Revert "Remove COMPILE_OPTS from Makefile"

This reverts commit 1f57795: these options are needed for plumbing
Ibex configs through. I've got a follow-up that does this more neatly,
but that depends on some other scripting changes so let's revert the
breakage for now.
This commit is contained in:
Rupert Swarbrick 2022-04-22 15:47:44 +01:00 committed by Rupert Swarbrick
parent 1c02f450d6
commit 5a9b5b9993
4 changed files with 17 additions and 5 deletions

View file

@ -40,6 +40,8 @@ OUT-SEED := $(OUT)/seed-$(SEED)
export dv_root := $(realpath ../../../vendor/lowrisc_ip/dv)
export DUT_TOP := dut
# Compile time options for ibex RTL simulation
COMPILE_OPTS +=
# Run time options for ibex RTL simulation
SIM_OPTS :=
# Enable waveform dumping
@ -157,6 +159,7 @@ include $(sim-cfg-mk)
.PHONY: test-cfg
test-cfg:
@echo "COMPILE_OPTS" $(COMPILE_OPTS)
@echo "SIM_OPTS" $(SIM_OPTS)
###############################################################################
@ -387,7 +390,7 @@ all-verilog = \
$(shell find ../../../rtl -name '*.v' -o -name '*.sv' -o -name '*.svh') \
$(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COSIM
tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS COSIM
-include $(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk
tb-compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(tb-compile-var-deps))
@ -405,7 +408,8 @@ $(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp: \
$(verb-arg) \
--output=$(OUT-DIR) \
--simulator=$(SIMULATOR) \
$(cov-arg) $(wave-arg) $(cosim-arg)
$(cov-arg) $(wave-arg) $(cosim-arg) \
--compile-opts="$(COMPILE_OPTS)"
$(call dump-vars,$(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk,comp,$(tb-compile-var-deps))
@touch $@

View file

@ -23,6 +23,7 @@
# gen_test : Test name used by the instruction generator
# asm_tests : Path to directed, hand-coded assembly test file or directory
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts : Options for the RTL & ISS trace comparison

View file

@ -21,6 +21,7 @@ def main() -> int:
parser.add_argument('--en_cov', action='store_true')
parser.add_argument('--en_wave', action='store_true')
parser.add_argument('--en_cosim', action='store_true')
parser.add_argument('--compile-opts', default='')
args = parser.parse_args()
@ -35,7 +36,11 @@ def main() -> int:
compile_cmds, _ = get_simulator_cmd(args.simulator, enables)
for pre_cmd in compile_cmds:
cmd = subst_vars(pre_cmd, {'out': output_dir})
cmd = subst_vars(pre_cmd,
{
'out': output_dir,
'cmp_opts': args.compile_opts
})
retcode = run_one(args.verbose, ['sh', '-c', cmd],
discard_stdstreams=True)
if retcode:

View file

@ -32,7 +32,7 @@
-debug_access+pp
-xlrm uniq_prior_final
-CFLAGS '--std=c99 -fno-extended-identifiers'
-lca -kdb <wave_opts> <cov_opts> <cosim_opts>"
-lca -kdb <cmp_opts> <wave_opts> <cov_opts> <cosim_opts>"
cov_opts: >
-cm line+tgl+assert+fsm+branch
-cm_tgl portsonly
@ -81,7 +81,7 @@
+define+UVM
-timescale \"1 ns / 1 ps \"
-writetoplevels <out>/top.list
-l <out>/compile.log"
-l <out>/compile.log <cmp_opts>"
sim:
cmd: >
vsim -64 -c <cov_opts> -do "run -a; quit -f" +designfile -f <out>/top.list <sim_opts> -sv_seed <seed> +access +r+w +UVM_TESTNAME=<rtl_test> +UVM_VERBOSITY=UVM_LOW +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log
@ -116,6 +116,7 @@
cmd:
- "vlib <out>/work"
- "vlog -work <out>/work
<cmp_opts>
-uvmver 1.2
+define+UVM
-f ibex_dv.f"
@ -159,6 +160,7 @@
-elaborate
-l <out>/compile.log
-xmlibdirpath <out>
<cmp_opts>
<cov_opts>
<wave_opts>"
cov_opts: >