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Remove non-ASCII characters from .sv and .rst files

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Pirmin Vogel 2019-10-10 09:41:11 +01:00
parent 5972c63ba8
commit 5f0be50473
3 changed files with 4 additions and 5 deletions
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3
doc/verification.rst
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@ -44,8 +44,7 @@ End-to-end RTL/ISS co-simulation flow
RTL/ISS co-simulation flow chart
The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here’s the list of frequently
used commands:
The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here is the list of frequently used commands:
.. code-block:: bash

2
rtl/ibex_controller.sv
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@ -527,7 +527,7 @@ module ibex_controller (
* to be transferred back to a debugging environment. It
* generates a breakpoint exception and performs no other
* operation. [...] ECALL and EBREAK cause the receiving
* privilege mode’s epc register to be set to the address of the
* privilege mode's epc register to be set to the address of the
* ECALL or EBREAK instruction itself, not the address of the
* following instruction." [Privileged Spec v1.11, p.40]
*/

4
vendor/google_riscv-dv/src/riscv_instr_base.sv vendored
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@ -123,7 +123,7 @@ class riscv_instr_base extends uvm_object;
}
}
// Registers specified by the three-bit rs1’, rs2’, and rd’ fields of the CIW, CL, CS,
// Registers specified by the three-bit rs1', rs2', and rd' fields of the CIW, CL, CS,
// and CB formats
constraint compressed_three_bits_csr_c {
if(format inside {CIW_FORMAT, CL_FORMAT, CS_FORMAT, CB_FORMAT}) {
@ -168,7 +168,7 @@ class riscv_instr_base extends uvm_object;
}
constraint rvc_csr_c {
// Registers specified by the three-bit rs1’, rs2’, and rd’ fields of the CIW, CL, CS,
// Registers specified by the three-bit rs1', rs2', and rd' fields of the CIW, CL, CS,
// and CB formats
if(format inside {CIW_FORMAT, CL_FORMAT, CS_FORMAT, CB_FORMAT}) {
rs1 inside {[S0:A5]};