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Remove all case inside from decoder
This commit is contained in:
Sven Stucki
parent
2c93147fc3
commit
5f3b73ab8a
1 changed files with 60 additions and 95 deletions
155
controller.sv
155
controller.sv
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@ -293,13 +293,13 @@ module controller
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rega_used = 1'b1;
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regb_used = 1'b1;
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unique case (instr_rdata_i) inside
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`INSTR_BEQ: alu_operator = `ALU_EQ;
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`INSTR_BNE: alu_operator = `ALU_NE;
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`INSTR_BLT: alu_operator = `ALU_LTS;
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`INSTR_BGE: alu_operator = `ALU_GES;
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`INSTR_BLTU: alu_operator = `ALU_LTU;
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`INSTR_BGEU: alu_operator = `ALU_GEU;
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unique case (instr_rdata_i[14:12])
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3'b000: alu_operator = `ALU_EQ;
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3'b001: alu_operator = `ALU_NE;
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3'b100: alu_operator = `ALU_LTS;
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3'b101: alu_operator = `ALU_GES;
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3'b110: alu_operator = `ALU_LTU;
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3'b111: alu_operator = `ALU_GEU;
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default: begin
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illegal_insn_int = 1'b1;
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@ -422,54 +422,6 @@ module controller
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end
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end
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/*
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// Pre/Post-Increment Stores and Register-Register Stores
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`OPCODE_STPOST, `OPCODE_STPRE: begin
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alu_operator = `ALU_ADD; // addr is generated in ID stage so no need for addr gen in alu TODO: always use ID stage addr
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data_req = 1'b1;
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regfile_alu_waddr_mux_sel_o = 2'b00;
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rega_used = 1'b1;
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regb_used = 1'b1;
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data_we = 1'b1; // write to memory
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if (instr_rdata_i[31:26] == `OPCODE_STPOST)
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begin
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prepost_useincr_o = 1'b0; // if post increment instruction, don't use the modified address
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end
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case (instr_rdata_i[5:4])
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default: begin
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_5N6S; // offset in 11bit immediate
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regfile_alu_we = 1'b1; // write new addr value into regfile using portB
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end
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2'b11: begin // register-register store with post increment
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regc_used = 1'b1;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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regfile_alu_we = 1'b1; // write new addr value into regfile using portB
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end
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2'b01: begin // register-register store without pre/post-increment
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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regc_used = 1'b1;
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end
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endcase // case (instr_rdata_i[5:4])
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// Word, Half Word or Byte store
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case (instr_rdata_i[3:2])
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default: data_type_o = 2'b00;
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2'b00: data_type_o = 2'b00; // word
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2'b10: data_type_o = 2'b01; // half word
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2'b11: data_type_o = 2'b10; // byte
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endcase // case(instr_rdata_i[4:3]
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// offset inside value to be stored, e.g. l.sh1, l.sb1 and so on
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data_reg_offset_o = instr_rdata_i[1:0];
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end
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*/
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//////////////////////////
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// _ _ _ _ //
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@ -502,21 +454,31 @@ module controller
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regfile_alu_we = 1'b1;
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rega_used = 1'b1;
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unique case (instr_rdata_i) inside
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`INSTR_ADDI: alu_operator = `ALU_ADD; // Add Immediate
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`INSTR_SLTI: alu_operator = `ALU_SLTS; // Set to one if Lower Than Immediate
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`INSTR_SLTIU: alu_operator = `ALU_SLTU; // Set to one if Lower Than Immediate Unsigned
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`INSTR_XORI: alu_operator = `ALU_XOR; // Exclusive Or with Immediate
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`INSTR_ORI: alu_operator = `ALU_OR; // Or with Immediate
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`INSTR_ANDI: alu_operator = `ALU_AND; // And with Immediate
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`INSTR_SLLI: alu_operator = `ALU_SLL; // Shift Left Logical by Immediate
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`INSTR_SRLI: alu_operator = `ALU_SRL; // Shift Right Logical by Immediate
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`INSTR_SRAI: alu_operator = `ALU_SRA; // Shift Right Arithmetically by Immediate
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default: begin
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regfile_alu_we = 1'b0;
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illegal_insn_int = 1'b1;
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unique case (instr_rdata_i[14:12])
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3'b000: alu_operator = `ALU_ADD; // Add Immediate
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3'b010: alu_operator = `ALU_SLTS; // Set to one if Lower Than Immediate
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3'b011: alu_operator = `ALU_SLTU; // Set to one if Lower Than Immediate Unsigned
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3'b100: alu_operator = `ALU_XOR; // Exclusive Or with Immediate
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3'b110: alu_operator = `ALU_OR; // Or with Immediate
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3'b111: alu_operator = `ALU_AND; // And with Immediate
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3'b001: begin
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alu_operator = `ALU_SLL; // Shift Left Logical by Immediate
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if (instr_rdata_i[31:25] != 7'b0)
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illegal_insn_int = 1'b1;
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end
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endcase // unique case (instr_rdata_i)
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3'b101: begin
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if (instr_rdata_i[31:25] == 7'b0)
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alu_operator = `ALU_SRL; // Shift Right Logical by Immediate
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else if (instr_rdata_i[31:25] == 7'b010_0000)
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alu_operator = `ALU_SRA; // Shift Right Arithmetically by Immediate
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else
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illegal_insn_int = 1'b1;
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end
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default: illegal_insn_int = 1'b1;
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endcase
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end
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`OPCODE_OP: begin // Register-Register ALU operation
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@ -524,19 +486,22 @@ module controller
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rega_used = 1'b1;
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regb_used = 1'b1;
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unique case (instr_rdata_i) inside
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`INSTR_ADD: alu_operator = `ALU_ADD; // Add
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`INSTR_SUB: alu_operator = `ALU_SUB; // Sub
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`INSTR_SLL: alu_operator = `ALU_SLL; // Shift Left Logical
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`INSTR_SLT: alu_operator = `ALU_SLTS; // Set Lower Than
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`INSTR_SLTU: alu_operator = `ALU_SLTU; // Set Lower Than Unsigned
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`INSTR_XOR: alu_operator = `ALU_XOR; // Xor
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`INSTR_SRL: alu_operator = `ALU_SRL; // Shift Right Logical
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`INSTR_SRA: alu_operator = `ALU_SRA; // Shift Right Arithmetic
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`INSTR_OR: alu_operator = `ALU_OR; // Or
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`INSTR_AND: alu_operator = `ALU_AND; // And
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unique case ({instr_rdata_i[31:25], instr_rdata_i[14:12]})
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{7'b000_0000, 3'b000}: alu_operator = `ALU_ADD; // Add
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{7'b010_0000, 3'b000}: alu_operator = `ALU_SUB; // Sub
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`INSTR_MUL: mult_en = 1'b1; // Multiplication
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{7'b000_0000, 3'b010}: alu_operator = `ALU_SLTS; // Set Lower Than
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{7'b000_0000, 3'b011}: alu_operator = `ALU_SLTU; // Set Lower Than Unsigned
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{7'b000_0000, 3'b100}: alu_operator = `ALU_XOR; // Xor
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{7'b000_0000, 3'b110}: alu_operator = `ALU_OR; // Or
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{7'b000_0000, 3'b111}: alu_operator = `ALU_AND; // And
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{7'b000_0000, 3'b001}: alu_operator = `ALU_SLL; // Shift Left Logical
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{7'b000_0000, 3'b101}: alu_operator = `ALU_SRL; // Shift Right Logical
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{7'b010_0000, 3'b101}: alu_operator = `ALU_SRA; // Shift Right Arithmetic
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{7'b000_0001, 3'b000}: mult_en = 1'b1; // Multiplication
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default: begin
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regfile_alu_we = 1'b0;
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@ -547,16 +512,6 @@ module controller
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/*
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`OPCODE_MULI: begin // Multiply Immediate Signed
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_16;
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mult_is_running = 1'b1;
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regfile_alu_we = 1'b1;
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regfile_alu_waddr_mux_sel_o = 2'b01;
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rega_used = 1'b1;
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end
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`OPCODE_ALU: begin // Arithmetic Operation
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rega_used = 1'b1;
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regb_used = 1'b1;
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@ -852,21 +807,27 @@ module controller
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if (instr_rdata_i[14:12] == 3'b000)
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begin
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// non CSR related SYSTEM instructions
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unique case (instr_rdata_i) inside
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`INSTR_EBREAK:
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unique case (instr_rdata_i[31:0])
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32'h00_00_00_73: // ECALL
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begin
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// environment (system) call
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// TODO: Handle in controller
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end
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32'h00_10_00_73: // EBREAK
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begin
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// debugger trap
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trap_insn_o = 1'b1;
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end
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`INSTR_ERET:
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32'h10_00_00_73: // ERET
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begin
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// TODO: Handle in controller
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//pc_mux_sel = `PC_ERET;
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clear_isr_running_o = 1'b1;
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end
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`INSTR_WFI:
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32'h10_20_00_73: // WFI
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begin
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// flush pipeline
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pipe_flush_o = 1'b1;
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@ -1202,6 +1163,10 @@ module controller
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if (ctrl_fsm_cs != DECODE)
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deassert_we = 1'b1;
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// deassert WE in case of illegal instruction
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if (illegal_insn_int)
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deassert_we = 1'b1;
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// Stall because of load operation
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if ((data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) &&
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((reg_d_ex_is_reg_a_id == 1'b1) || (reg_d_ex_is_reg_b_id == 1'b1) || (reg_d_ex_is_reg_c_id == 1'b1)) )
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