github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 04:47:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Make illegal insn warning less verbose in simulation

Browse source
This commit is contained in:
Sven Stucki 2015-08-26 19:12:25 +02:00
parent a18972db26
commit 685b6dbabb
1 changed files with 10 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

16
controller.sv
View file

@ -987,6 +987,16 @@ module controller
end
endcase
// synopsys translate_off
// print warning in case of decoding errors
// note: this is done intentionally before checking RVC decoding, to
// suppress wrong (and annoying) messages during simulation
if (illegal_insn_int) begin
$warning("Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
//prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
end
// synopsys translate_on
// make sure invalid compressed instruction causes an exception
if (illegal_c_insn_i) begin
illegal_insn_int = 1'b1;
@ -1093,12 +1103,6 @@ module controller
// handle illegal instructions
if (illegal_insn_int) begin
illegal_insn_o = 1'b1;
// synopsys translate_off
$display("%t: Illegal instruction (core %0d) at PC 0x%h", $time, riscv_core.core_id_i,
id_stage.current_pc_id_i);
//prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
// synopsys translate_on
end
// the pipeline is flushed and we are requested to go to sleep