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Merge in all changes from RI5CY core

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Markus Wegmann 2016-12-07 13:36:44 +01:00
commit 6a969e6431
2 changed files with 0 additions and 7 deletions
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1
alu.sv
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@ -472,7 +472,6 @@ module riscv_alu
assign clip_is_lower_neg = adder_result[31];
assign clip_is_lower_u = (operator_i == ALU_CLIPU) && operand_a_i[31];
//assign clip_result = clip_is_lower_u ? '0 : (clip_is_lower_neg ? operand_b_neg : result_minmax);
assign clip_result = is_greater ? result_minmax: (clip_is_lower_u ? '0 : (clip_is_lower_neg ? operand_b_neg : result_minmax));
//////////////////////////////////////////////////
// ____ _ _ _ _ _____ _____ _ _____ //

6
decoder.sv
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@ -141,9 +141,6 @@ module riscv_decoder
logic [1:0] csr_op;
logic davide;
/////////////////////////////////////////////
// ____ _ //
// | _ \ ___ ___ ___ __| | ___ _ __ //
@ -227,10 +224,8 @@ module riscv_decoder
bmask_b_mux_o = BMASK_B_ZERO;
alu_bmask_a_mux_sel_o = BMASK_A_IMM;
alu_bmask_b_mux_sel_o = BMASK_B_IMM;
davide = '0;
`endif // BIT_SUPPORT
unique case (instr_rdata_i[6:0])
//////////////////////////////////////
@ -548,7 +543,6 @@ module riscv_decoder
3'b100: begin
alu_operator_o = ALU_BSET;
davide = 1'b1;
if (~instr_rdata_i[30]) begin
//register variant
regb_used_o = 1'b1;