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Rename mux select signals, allow for more aggressive optimizations in if
stage
This commit is contained in:
Andreas Traber
parent
e5bb1447cc
commit
6ba66dc141
4 changed files with 39 additions and 32 deletions
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@ -59,15 +59,15 @@ module riscv_controller
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output logic instr_req_o, // Start fetching instructions
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// to prefetcher
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output logic pc_set_o, // jump to address set by pc_mux_sel
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output logic [2:0] pc_mux_sel_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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output logic pc_set_o, // jump to address set by pc_mux
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output logic [2:0] pc_mux_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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// LSU
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input logic data_req_ex_i, // data memory access is currently performed in EX stage
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input logic data_misaligned_i,
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// hwloop signals
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input logic hwloop_jump_i, // modify pc_mux_sel to select the hwloop addr
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input logic hwloop_jump_i, // modify pc_mux to select the hwloop addr
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// jump/branch signals
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input logic branch_taken_ex_i, // branch taken signal from EX ALU
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@ -173,7 +173,7 @@ module riscv_controller
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save_pc_if_o = 1'b0;
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save_pc_id_o = 1'b0;
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pc_mux_sel_o = `PC_BOOT;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b0;
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ctrl_fsm_ns = ctrl_fsm_cs;
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@ -200,7 +200,7 @@ module riscv_controller
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BOOT_SET:
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begin
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instr_req_o = 1'b1;
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pc_mux_sel_o = `PC_BOOT;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = FIRST_FETCH;
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@ -231,13 +231,13 @@ module riscv_controller
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// hwloop detected, jump to start address!
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// Attention: This has to be done in the DECODE and the FIRST_FETCH states
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if (hwloop_jump_i == 1'b1) begin
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pc_mux_sel_o = `PC_HWLOOP;
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pc_mux_o = `PC_HWLOOP;
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pc_set_o = 1'b1;
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end
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// handle exceptions
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if (exc_req_i) begin
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pc_mux_sel_o = `PC_EXCEPTION;
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pc_mux_o = `PC_EXCEPTION;
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pc_set_o = 1'b1;
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exc_ack_o = 1'b1;
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@ -268,7 +268,7 @@ module riscv_controller
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// we don't need to worry about conditional branches here as they
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// will be evaluated in the EX stage
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if (jump_in_dec_i == `BRANCH_JALR || jump_in_dec_i == `BRANCH_JAL) begin
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pc_mux_sel_o = `PC_JUMP;
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pc_mux_o = `PC_JUMP;
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// if there is a jr stall, wait for it to be gone
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if (~jr_stall_o)
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@ -281,13 +281,13 @@ module riscv_controller
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// handle hwloops
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if (hwloop_jump_i) begin
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pc_mux_sel_o = `PC_HWLOOP;
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pc_set_o = 1'b1;
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pc_mux_o = `PC_HWLOOP;
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pc_set_o = 1'b1;
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end
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if (eret_insn_i) begin
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pc_mux_sel_o = `PC_ERET;
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pc_set_o = 1'b1;
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pc_mux_o = `PC_ERET;
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pc_set_o = 1'b1;
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end
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// handle WFI instruction, flush pipeline and (potentially) go to
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@ -309,7 +309,7 @@ module riscv_controller
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begin
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ctrl_fsm_ns = JUMP_EXC;
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end else begin
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pc_mux_sel_o = `PC_EXCEPTION;
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pc_mux_o = `PC_EXCEPTION;
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pc_set_o = 1'b1;
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exc_ack_o = 1'b1;
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@ -347,7 +347,7 @@ module riscv_controller
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// handle conditional branches
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if (branch_taken_ex_i) begin
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// there is a branch in the EX stage that is taken
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pc_mux_sel_o = `PC_BRANCH;
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pc_mux_o = `PC_BRANCH;
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pc_set_o = 1'b1;
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is_decoding_o = 1'b0; // we are not decoding the current instruction in the ID stage
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@ -369,8 +369,8 @@ module riscv_controller
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if (branch_taken_ex_i) begin
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// there is a branch in the EX stage that is taken
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pc_mux_sel_o = `PC_BRANCH;
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pc_set_o = 1'b1;
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pc_mux_o = `PC_BRANCH;
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pc_set_o = 1'b1;
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end
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ctrl_fsm_ns = DBG_SIGNAL;
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@ -393,7 +393,7 @@ module riscv_controller
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halt_if_o = 1'b1;
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if(dbg_set_npc_i == 1'b1) begin
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pc_mux_sel_o = `PC_DBG_NPC;
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pc_mux_o = `PC_DBG_NPC;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT;
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end
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@ -436,7 +436,7 @@ module riscv_controller
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// we can just save the IF PC, since it propagated through the
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// prefetcher
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save_pc_if_o = 1'b1;
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pc_mux_sel_o = `PC_EXCEPTION;
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pc_mux_o = `PC_EXCEPTION;
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pc_set_o = 1'b1;
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exc_ack_o = 1'b1;
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@ -62,7 +62,7 @@ module riscv_id_stage
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// IF and ID stage signals
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output logic clear_instr_valid_o,
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output logic pc_set_o,
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output logic [2:0] pc_mux_sel_o,
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output logic [2:0] pc_mux_o,
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output logic [1:0] exc_pc_mux_o,
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output logic [4:0] exc_vec_pc_mux_o,
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@ -654,7 +654,7 @@ module riscv_id_stage
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// to prefetcher
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.pc_set_o ( pc_set_o ),
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.pc_mux_sel_o ( pc_mux_sel_o ),
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.pc_mux_o ( pc_mux_o ),
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// LSU
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.data_req_ex_i ( data_req_ex_o ),
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25
if_stage.sv
25
if_stage.sv
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@ -66,7 +66,7 @@ module riscv_if_stage
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input logic clear_instr_valid_i, // clear instruction valid bit in IF/ID pipe
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input logic pc_set_i, // set the program counter to a new value
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input logic [31:0] exception_pc_reg_i, // address used to restore PC when the interrupt/exception is served
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input logic [2:0] pc_mux_sel_i, // sel for pc multiplexer
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input logic [2:0] pc_mux_i, // sel for pc multiplexer
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input logic [1:0] exc_pc_mux_i, // selects ISR address
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input logic [4:0] exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines
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@ -125,8 +125,8 @@ module riscv_if_stage
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always_comb
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begin
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// default values for regular aligned access
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instr_rdata_int = fetch_rdata;
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current_pc_if_o = {fetch_addr[31:2], 2'b00};
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instr_rdata_int = fetch_rdata;
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if (unaligned) begin
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current_pc_if_o = {fetch_addr[31:2], 2'b10};
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@ -143,20 +143,28 @@ module riscv_if_stage
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// exception PC selection mux
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always_comb
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begin : EXC_PC_MUX
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exc_pc = 'x;
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unique case (exc_pc_mux_i)
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`EXC_PC_ILLINSN: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ILLINSN };
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`EXC_PC_ECALL: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ECALL };
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`EXC_PC_LOAD: exc_pc = { boot_addr_i[31:8], `EXC_OFF_LSUERR };
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`EXC_PC_IRQ: exc_pc = { boot_addr_i[31:8], 1'b0, exc_vec_pc_mux_i[4:0], 2'b0 };
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// TODO: Add case for EXC_PC_STORE as soon as it differs from load
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default: exc_pc = { boot_addr_i[31:8], `EXC_OFF_ILLINSN };
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default: begin
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// synopsys translate_off
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$display("%t: Illegal exc pc_mux value (%0d)!", $time, exc_pc_mux_i);
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// synopsys translate_on
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end
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endcase
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end
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// fetch address selection
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always_comb
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begin
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unique case (pc_mux_sel_i)
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fetch_addr_n = 'x;
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unique case (pc_mux_i)
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`PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], `EXC_OFF_RST};
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`PC_JUMP: fetch_addr_n = {jump_target_id_i[31:2], 2'b0};
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`PC_BRANCH: fetch_addr_n = {jump_target_ex_i[31:2], 2'b0};
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@ -164,11 +172,10 @@ module riscv_if_stage
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`PC_ERET: fetch_addr_n = exception_pc_reg_i; // PC is restored when returning from IRQ/exception
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`PC_HWLOOP: fetch_addr_n = hwloop_target_i; // PC is taken from hwloop start addr
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`PC_DBG_NPC: fetch_addr_n = dbg_npc_i; // PC is taken from debug unit
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default:
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begin
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fetch_addr_n = 'X;
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default: begin
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// synopsys translate_off
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$display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_sel_i);
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$display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_i);
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// synopsys translate_on
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end
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endcase
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@ -178,7 +185,7 @@ module riscv_if_stage
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begin
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unaligned_jump = 1'b0;
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case (pc_mux_sel_i)
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case (pc_mux_i)
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`PC_JUMP: unaligned_jump = jump_target_id_i[1];
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`PC_BRANCH: unaligned_jump = jump_target_ex_i[1];
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`PC_ERET: unaligned_jump = exception_pc_reg_i[1];
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@ -94,7 +94,7 @@ module riscv_core
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logic clear_instr_valid;
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logic pc_set;
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logic [2:0] pc_mux_sel_id; // Mux selector for next PC
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logic [2:0] pc_mux_id; // Mux selector for next PC
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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logic [4:0] exc_vec_pc_mux_id; // Mux selector for vectorized IR lines
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@ -266,7 +266,7 @@ module riscv_core
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.clear_instr_valid_i ( clear_instr_valid ),
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( epcr ), // exception return address
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.pc_mux_sel_i ( pc_mux_sel_id ), // sel for pc multiplexer
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.pc_mux_i ( pc_mux_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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@ -326,7 +326,7 @@ module riscv_core
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// IF and ID control signals
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.clear_instr_valid_o ( clear_instr_valid ),
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.pc_set_o ( pc_set ),
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.pc_mux_sel_o ( pc_mux_sel_id ),
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.pc_mux_o ( pc_mux_id ),
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.exc_vec_pc_mux_o ( exc_vec_pc_mux_id ),
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