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optimized decoder-controller branch-jump signals

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Pasquale Davide Schiavone 2017-03-28 10:56:16 +02:00
parent 0eba7ea82c
commit 6c679d41c4
3 changed files with 24 additions and 18 deletions
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2
zeroriscy_core.sv
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@ -686,7 +686,7 @@ module zeroriscy_core
.id_valid ( id_stage_i.id_valid_o ),
.is_decoding ( id_stage_i.is_decoding_o ),
.is_branch ( id_stage_i.branch_in_id ),
.branch_taken ( id_stage_i.branch_set ),
.branch_taken ( id_stage_i.branch_set_q ),
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
.rs1_value ( id_stage_i.operand_a_fw_id ),

10
zeroriscy_decoder.sv
View file

@ -40,8 +40,8 @@ module zeroriscy_decoder
// singals running to/from controller
input logic deassert_we_i, // deassert we, we are stalled or not active
input logic data_misaligned_i, // misaligned data load/store in progress
input logic branch_set_i,
input logic jump_set_i,
input logic branch_mux_i,
input logic jump_mux_i,
output logic illegal_insn_o, // illegal instruction encountered
output logic ebrk_insn_o, // trap instruction encountered
output logic mret_insn_o, // return from exception instruction encountered
@ -157,7 +157,7 @@ module zeroriscy_decoder
OPCODE_JAL: begin // Jump and Link
jump_in_id = 1'b1;
if(jump_set_i) begin
if(jump_mux_i) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_CURRPC;
alu_op_b_mux_sel_o = OP_B_IMM;
@ -176,7 +176,7 @@ module zeroriscy_decoder
OPCODE_JALR: begin // Jump and Link Register
jump_in_id = 1'b1;
if(jump_set_i) begin
if(jump_mux_i) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
alu_op_b_mux_sel_o = OP_B_IMM;
@ -203,7 +203,7 @@ module zeroriscy_decoder
branch_in_id = 1'b1;
if (~branch_set_i)
if (branch_mux_i)
begin
unique case (instr_rdata_i[14:12])
3'b000: alu_operator_o = ALU_EQ;

30
zeroriscy_id_stage.sv
View file

@ -170,9 +170,11 @@ module zeroriscy_id_stage
logic branch_taken_ex;
logic branch_in_id;
logic branch_in_id_q;
logic branch_set;
logic branch_set_n;
logic branch_set_q;
logic branch_mux_dec;
logic jump_set;
logic jump_mux_dec;
logic jump_in_id;
logic instr_multicyle;
@ -212,7 +214,7 @@ module zeroriscy_id_stage
logic [4:0] regfile_addr_rb_id;
logic [4:0] regfile_alu_waddr_id;
logic regfile_we_id;
logic regfile_we_id;
logic [31:0] regfile_data_ra_id;
logic [31:0] regfile_data_rb_id;
@ -455,8 +457,8 @@ module zeroriscy_id_stage
// controller related signals
.deassert_we_i ( deassert_we ),
.data_misaligned_i ( data_misaligned_i ),
.branch_set_i ( branch_set ),
.jump_set_i ( jump_set ),
.branch_mux_i ( branch_mux_dec ),
.jump_mux_i ( jump_mux_dec ),
.illegal_insn_o ( illegal_insn_dec ),
.ebrk_insn_o ( ebrk_insn ),
@ -540,7 +542,7 @@ module zeroriscy_id_stage
// jump/branch control
.branch_in_id_i ( branch_in_id ),
.branch_taken_ex_i ( branch_taken_ex ),
.branch_set_i ( branch_set ),
.branch_set_i ( branch_set_q ),
.jump_set_i ( jump_set ),
.jump_in_id_i ( jump_in_id ),
@ -664,12 +666,12 @@ module zeroriscy_id_stage
begin : EX_WB_Pipeline_Register
if (~rst_n)
begin
id_wb_fsm_cs <= IDLE;
branch_in_id_q <= 1'b0;
id_wb_fsm_cs <= IDLE;
branch_set_q <= 1'b0;
end
else begin
id_wb_fsm_cs <= id_wb_fsm_ns;
branch_in_id_q <= branch_in_id;
id_wb_fsm_cs <= id_wb_fsm_ns;
branch_set_q <= branch_set_n;
end
end
@ -687,13 +689,17 @@ module zeroriscy_id_stage
branch_stall = 1'b0;
select_data_rf = RF_EX;
instr_multicyle = 1'b0;
branch_set = 1'b0;
branch_set_n = 1'b0;
branch_mux_dec = 1'b0;
jump_set = 1'b0;
jump_mux_dec = 1'b0;
unique case (id_wb_fsm_cs)
IDLE:
begin
jump_mux_dec = 1'b1;
branch_mux_dec = 1'b1;
unique case (1'b1)
data_req_id: begin
//LSU operation
@ -707,6 +713,7 @@ module zeroriscy_id_stage
id_wb_fsm_ns = branch_decision_i ? WAIT_MULTICYCLE : IDLE;
branch_stall = branch_decision_i;
instr_multicyle = branch_decision_i;
branch_set_n = branch_decision_i;
end
multdiv_int_en: begin
//MUL or DIV operation
@ -729,7 +736,6 @@ module zeroriscy_id_stage
WAIT_MULTICYCLE:
begin
branch_set = branch_in_id_q;
if(ex_ready_i) begin
regfile_we = regfile_we_id;
id_wb_fsm_ns = IDLE;