github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 04:47:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix hwloop code indentation

Browse source
This commit is contained in:
Sven Stucki 2015-08-31 00:00:21 +02:00
parent 3c89d1400d
commit 6cdfde93c7
2 changed files with 62 additions and 61 deletions
Download patch file Download diff file Expand all files Collapse all files

87
hwloop_controller.sv
View file

@ -31,60 +31,61 @@
`include "defines.sv"
module hwloop_controller
(
(
// from id stage
input logic enable_i,
input logic [31:0] current_pc_i,
// from id stage
input logic enable_i,
input logic [31:0] current_pc_i,
// from hwloop_regs
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i,
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_i,
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_i,
// from hwloop_regs
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i,
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_i,
input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_i,
// to hwloop_regs
output logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_o,
// to hwloop_regs
output logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_o,
// to id stage
output logic hwloop_jump_o,
output logic [31:0] hwloop_targ_addr_o
);
// to id stage
output logic hwloop_jump_o,
output logic [31:0] hwloop_targ_addr_o
);
logic [`HWLOOP_REGS-1:0] pc_is_end_addr;
logic [`HWLOOP_REGS-1:0] pc_is_end_addr;
// generate comparators. check for end address and the loop counter
genvar i;
for (i = 0; i < `HWLOOP_REGS; i++) begin
assign pc_is_end_addr[i] = ((current_pc_i == hwloop_end_addr_i[i]) & (enable_i) & (hwloop_counter_i[i] > 32'b1)) ? 1'b1 : 1'b0;
end
genvar i;
for (i = 0; i < `HWLOOP_REGS; i++) begin
assign pc_is_end_addr[i] = ((current_pc_i == hwloop_end_addr_i[i]) & (enable_i) & (hwloop_counter_i[i] > 32'b1)) ? 1'b1 : 1'b0;
end
// output signal for ID stage
assign hwloop_jump_o = |pc_is_end_addr;
// output signal for ID stage
assign hwloop_jump_o = |pc_is_end_addr;
// select corresponding start address and decrement counter. give highest priority to register 0
always_comb begin
hwloop_targ_addr_o = 32'b0;
hwloop_dec_cnt_o = `HWLOOP_REGS'b0;
if (pc_is_end_addr[0]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[0];
hwloop_dec_cnt_o[0] = 1'b1;
end
else if (pc_is_end_addr[1]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[1];
hwloop_dec_cnt_o[1] = 1'b1;
end
// select corresponding start address and decrement counter. give highest priority to register 0
always_comb begin
hwloop_targ_addr_o = 32'b0;
hwloop_dec_cnt_o = `HWLOOP_REGS'b0;
if (pc_is_end_addr[0]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[0];
hwloop_dec_cnt_o[0] = 1'b1;
end
else if (pc_is_end_addr[1]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[1];
hwloop_dec_cnt_o[1] = 1'b1;
end
/* -----\/----- EXCLUDED -----\/-----
else if (pc_is_end_addr[2]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[2];
hwloop_dec_cnt_o[2] = 1'b1;
end
else if (pc_is_end_addr[3]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[3];
hwloop_dec_cnt_o[3] = 1'b1;
end
else if (pc_is_end_addr[2]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[2];
hwloop_dec_cnt_o[2] = 1'b1;
end
else if (pc_is_end_addr[3]) begin
hwloop_targ_addr_o = hwloop_start_addr_i[3];
hwloop_dec_cnt_o[3] = 1'b1;
end
-----/\----- EXCLUDED -----/\----- */
end
end
endmodule

36
hwloop_regs.sv
View file

@ -31,28 +31,28 @@
`include "defines.sv"
module hwloop_regs
(
input logic clk,
input logic rst_n,
(
input logic clk,
input logic rst_n,
// from ex stage
input logic [31:0] hwloop_start_data_i,
input logic [31:0] hwloop_end_data_i,
input logic [31:0] hwloop_cnt_data_i,
input logic [2:0] hwloop_we_i,
input logic [1:0] hwloop_regid_i, // selects the register set
// from ex stage
input logic [31:0] hwloop_start_data_i,
input logic [31:0] hwloop_end_data_i,
input logic [31:0] hwloop_cnt_data_i,
input logic [2:0] hwloop_we_i,
input logic [1:0] hwloop_regid_i, // selects the register set
// from controller
input logic stall_id_i,
// from controller
input logic stall_id_i,
// from hwloop controller
input logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_i,
// from hwloop controller
input logic [`HWLOOP_REGS-1:0] hwloop_dec_cnt_i,
// to hwloop controller
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_o,
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_o,
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_o
);
// to hwloop controller
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_o,
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_addr_o,
output logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_o
);
logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_regs_q;