This commit is contained in:
Markus Wegmann 2017-01-09 18:47:37 +01:00
parent 18000c5b90
commit 6eeeb11b8e

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@ -1781,9 +1781,9 @@ module riscv_id_stage
// stall control
// CONFIG_REGION: ONLY_ALIGNED
`ifdef ONLY_ALIGNED
assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & ex_ready_i);
`else
assign id_ready_o = ((~jr_stall) & (~load_stall) & ex_ready_i);
`else
assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & ex_ready_i);
`endif // ONLY_ALIGNED