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synced 2025-04-23 13:27:10 -04:00
Working on debug support
Most features have a preliminary support now, i.e. software breakpoints work in general, NPC and PPC SPR are integrated and fully working, so it is possible to set a new PC from the debugger There are probably still some bugs in corner cases, and I'm pretty sure jumps are not working nicely in single-stepping mode
This commit is contained in:
Andreas Traber
parent
102691a06a
commit
73dd948f59
4 changed files with 62 additions and 74 deletions
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@ -1254,7 +1254,10 @@ module controller
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case (dbg_fsm_cs)
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DBG_IDLE:
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begin
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if(trap_hit_i == 1'b1 && stall_ex_o == 1'b0 && jump_in_id_o == 2'b0)
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// branches take two cycles, jumps just one
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// everything else can be done immediately
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// TODO: there is a bug here, I'm sure of it
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if(trap_hit_i == 1'b1 && stall_ex_o == 1'b0 && jump_in_id_o == 2'b0 && jump_in_ex_i == 2'b0)
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begin
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dbg_halt = 1'b1;
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dbg_fsm_ns = DBG_EX;
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@ -58,11 +58,7 @@ module cs_registers
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output logic [31:0] hwlp_end_o,
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output logic [31:0] hwlp_counter_o,
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output logic [1:0] hwlp_regid_o,
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output logic [2:0] hwlp_we_o,
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// Signals for NPC register
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output logic [31:0] npc_o, // TODO: check if needed
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output logic set_npc_o // TODO: check if needed
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output logic [2:0] hwlp_we_o
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);
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@ -106,6 +102,11 @@ module cs_registers
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12'hF01: constant_rdata_int = 32'h00_00_80_00; // mimpid: PULP3, anonymous source (no allocated ID)
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12'hF10: constant_rdata_int = {22'b0, cluster_id_i, core_id_i}; // mhartid: unique hardware thread id
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// debug registers
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12'hFC0: constant_rdata_int = curr_pc_id_i; // Previous Program Counter for Debug
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12'h780: constant_rdata_int = curr_pc_if_i; // Next Program Counter for Debug
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default: is_constant = 1'b0;
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endcase
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end
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@ -57,25 +57,25 @@ module debug_unit
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output logic sp_mux_o,
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output logic regfile_mux_o,
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output logic regfile_we_o,
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output logic [15:0] regfile_addr_o,
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output logic [11:0] regfile_addr_o,
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output logic [31:0] regfile_wdata_o,
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input logic [31:0] regfile_rdata_i
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input logic [31:0] regfile_rdata_i,
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// Signals for NPC register
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output logic [31:0] npc_o,
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output logic set_npc_o
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);
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// registers for debug control
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logic [1:0] DSR_DP, DSR_DN; // Debug Stop Register: IIE, INTE
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logic [1:0] DMR1_DP, DMR1_DN; // only single step trace and branch trace bits
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logic [2*`N_WP-1:0] DMR2_DP, DMR2_DN; // only BP enable control and BP cause status
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// watchpoint status
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logic [`N_WP-1:0] WP_Status_D;
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// BP control FSM
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enum logic [2:0] {Idle, Trap, DebugStall, StallCore} BP_State_SN, BP_State_SP;
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// ack to debug interface
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assign dbginf_ack_o = (dbginf_strobe_i && (BP_State_SP == StallCore));
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assign dbginf_ack_o = dbginf_strobe_i && ((BP_State_SP == StallCore) || (dbginf_addr_i[15:11] == 5'b00110));
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always_comb
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begin
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@ -83,38 +83,32 @@ module debug_unit
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stall_core_o = 1'b0;
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dbginf_bp_o = 1'b0;
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flush_pipe_o = 1'b0;
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case (BP_State_SP)
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Idle:
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begin
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if(trap_i == 1'b1)
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BP_State_SN = Trap;
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if(dbginf_stall_i)
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begin
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dbginf_bp_o = 1'b1;
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stall_core_o = 1'b1;
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BP_State_SN = StallCore;
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end
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else if(dbginf_stall_i)
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begin
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flush_pipe_o = 1'b1;
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BP_State_SN = DebugStall;
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BP_State_SN = DebugStall;
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end
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end
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// A trap was encountered, wait for for the pipeline to be
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// flushed
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Trap:
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begin
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if(pipe_flushed_i == 1'b1)
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begin
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dbginf_bp_o = 1'b1;
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BP_State_SN = StallCore;
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end
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end
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// A stall from adv dbg was seen, flush the pipeline and wait for unstalling
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// A stall from adv dbg unit was seen, flush the pipeline and wait for unstalling
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DebugStall:
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begin
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flush_pipe_o = 1'b1;
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if(pipe_flushed_i == 1'b1)
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if(trap_i == 1'b1)
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begin
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BP_State_SN = StallCore;
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stall_core_o = 1'b1;
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BP_State_SN = StallCore;
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end
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end
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@ -137,15 +131,19 @@ module debug_unit
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assign dbg_st_en_o = DMR1_DP[0];
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assign dbg_dsr_o = DSR_DP;
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// handle set next program counter
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assign set_npc_o = (regfile_addr_o == 12'h780) && (sp_mux_o == 1'b1) && (regfile_we_o == 1'b1);
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assign npc_o = dbginf_data_i;
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// address decoding, write and read controller
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always_comb
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begin
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DMR1_DN = DMR1_DP;
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DMR2_DN[`N_WP-1:0] = DMR2_DP[`N_WP-1:0];
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DSR_DN = DSR_DP;
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dbginf_data_o = 32'b0;
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regfile_we_o = 1'b0;
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regfile_addr_o = 16'b0;
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regfile_addr_o = 'h0;
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regfile_mux_o = 1'b0;
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sp_mux_o = 1'b0;
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@ -160,13 +158,6 @@ module debug_unit
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else
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dbginf_data_o[`DMR1_ST+1:`DMR1_ST] = DMR1_DP;
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end
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11'd17: begin // SP_DMR2
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if(dbginf_we_i == 1'b1)
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DMR2_DN[`N_WP-1:0] = dbginf_data_i[`DMR2_WGB0 + (`N_WP-1):`DMR2_WGB0];
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else
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dbginf_data_o[`DMR2_WGB0 + (`N_WP-1):`DMR2_WGB0] = DMR2_DP[`N_WP-1:0];
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dbginf_data_o[`DMR2_WBS0 + (`N_WP-1):`DMR2_WBS0] = DMR2_DP[2*`N_WP-1:`N_WP];
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end
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11'd20: begin // SP_DSR
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// currently we only handle IIE and INTE
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if(dbginf_we_i == 1'b1)
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@ -177,27 +168,31 @@ module debug_unit
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default: ;
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endcase // casex [10:0]
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end
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// check if GPRs are accessed
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else if(dbginf_addr_i[15:10] == 6'b000001)
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// check if internal registers (GPR or SPR) are accessed
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else if(BP_State_SP == StallCore)
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begin
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regfile_mux_o = 1'b1;
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regfile_addr_o[4:0] = dbginf_addr_i[4:0];
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// check if GPRs are accessed
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if(dbginf_addr_i[15:10] == 6'b000001)
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begin
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regfile_mux_o = 1'b1;
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regfile_addr_o[4:0] = dbginf_addr_i[4:0];
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if(dbginf_we_i == 1'b1)
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regfile_we_o = 1'b1;
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if(dbginf_we_i == 1'b1)
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regfile_we_o = 1'b1;
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else
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dbginf_data_o = regfile_rdata_i;
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end
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// some other SPR is accessed
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else
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dbginf_data_o = regfile_rdata_i;
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end
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// some other SPR is accessed
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else
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begin
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sp_mux_o = 1'b1;
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regfile_addr_o = dbginf_addr_i;
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begin
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sp_mux_o = 1'b1;
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regfile_addr_o = dbginf_addr_i[11:0];
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if(dbginf_we_i == 1'b1)
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regfile_we_o = 1'b1;
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else
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dbginf_data_o = regfile_rdata_i;
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if(dbginf_we_i == 1'b1)
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regfile_we_o = 1'b1;
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else
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dbginf_data_o = regfile_rdata_i;
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end
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end
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end
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end
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@ -206,13 +201,11 @@ module debug_unit
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always_ff@(posedge clk or negedge rst_n) begin
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if (~rst_n) begin
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DMR1_DP <= 2'b0;
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DMR2_DP <= 'b0;
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DSR_DP <= 'b0;
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BP_State_SP <= Idle;
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end
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else begin
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DMR1_DP <= DMR1_DN;
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DMR2_DP <= DMR2_DN;
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DSR_DP <= DSR_DN;
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BP_State_SP <= BP_State_SN;
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end
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@ -236,12 +236,6 @@ module riscv_core
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`endif
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// TODO: Temporary assignments while not everything from OR10N is implemented (e.g. debug unit)
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assign dbg_dsr = 2'b0;
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assign dbg_st_en = 1'b0;
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assign dbg_sp_mux = 1'b0;
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assign dbg_flush_pipe = 1'b0;
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//////////////////////////////////////////////////
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// ___ _____ ____ _____ _ ____ _____ //
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@ -646,10 +640,7 @@ module riscv_core
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.save_pc_if_i ( save_pc_if ),
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.save_pc_id_i ( save_pc_id ),
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.epcr_o ( epcr ),
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.irq_enable_o ( irq_enable ),
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.npc_o ( dbg_npc ), // PC from debug unit
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.set_npc_o ( dbg_set_npc ) // set PC to new value
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.irq_enable_o ( irq_enable )
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);
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// Mux for SPR access through Debug Unit
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@ -747,6 +738,7 @@ module riscv_core
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assign hwlp_cnt_data = (hwlp_we_ex[2] == 1'b1) ? hwlp_cnt_data_ex : sp_hwlp_cnt;
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assign hwlp_regid = (|hwlp_we_ex) ? hwlp_regid_ex : sp_hwlp_regid;
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assign hwlp_we = hwlp_we_ex | sp_hwlp_we;
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*/
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/////////////////////////////////////////////////////////////
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@ -786,13 +778,12 @@ module riscv_core
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.regfile_we_o ( dbg_reg_we ),
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.regfile_addr_o ( dbg_reg_addr ),
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.regfile_wdata_o ( dbg_reg_wdata ),
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.regfile_rdata_i ( dbg_rdata )
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.regfile_rdata_i ( dbg_rdata ),
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.npc_o ( dbg_npc ), // PC from debug unit
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.set_npc_o ( dbg_set_npc ) // set PC to new value
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);
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*/
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assign dbg_reg_mux = 0;
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assign dbg_stall = 0;
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// Execution trace generation
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