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Pasquale Davide Schiavone 2018-09-28 10:45:23 +02:00
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*zero-riscy** is a small 2-stage RISC-V core derived from RI5CY.
**zero-riscy** fully implements the RV32IMC instruction set and a minimal
**zero-riscy** fully implements the RV32IMC instruction set and a minimal
set of RISCV privileged specifications.
**zero-riscy** can be configured to be very small by disabling the RV32M extensions
and by activating the RV32E extensios. This configuration is called **micro-riscy**
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## Documentation
A datasheet that explains the most important features of the core can be found
in the `zeroriscy-doc` repository.
in the doc folder.