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Additional code cleanup and defines
This commit is contained in:
Sven Stucki
parent
5e4db58f21
commit
85d2632a38
3 changed files with 46 additions and 46 deletions
78
if_stage.sv
78
if_stage.sv
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@ -99,18 +99,18 @@ module if_stage
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// Next PC Selection: pc_mux_sel_i comes from id_stage.controller
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always_comb
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begin : PC_MUX
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case (pc_mux_sel_i)
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`INCR_PC: begin next_pc = current_pc_if_o + 32'd4; end // PC is incremented and points the next instruction
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`NO_INCR: begin next_pc = current_pc_if_o; end // PC is not incremented
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`PC_FROM_REGFILE: begin next_pc = pc_from_regfile_i; end // PC is taken from the regfile
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`PC_FROM_IMM: begin next_pc = branch_taken; end // PC is taken from current PC in id + the immediate displacement
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`PC_EXCEPTION: begin next_pc = exc_pc; end // PC that points to the exception
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`EXC_PC_REG: begin next_pc = exception_pc_reg_i; end // restore the PC when exiting from interr/ecpetions
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`HWLOOP_ADDR: begin next_pc = pc_from_hwloop_i; end // PC is taken from hwloop start addr
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case (pc_mux_sel_i)
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`INCR_PC: begin next_pc = current_pc_if_o + 32'd4; end // PC is incremented and points the next instruction
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`NO_INCR: begin next_pc = current_pc_if_o; end // PC is not incremented
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`PC_FROM_REGFILE: begin next_pc = pc_from_regfile_i; end // PC is taken from the regfile
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`PC_FROM_IMM: begin next_pc = branch_taken; end // PC is taken from current PC in id + the immediate displacement
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`PC_EXCEPTION: begin next_pc = exc_pc; end // PC that points to the exception
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`EXC_PC_REG: begin next_pc = exception_pc_reg_i; end // restore the PC when exiting from interr/ecpetions
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`HWLOOP_ADDR: begin next_pc = pc_from_hwloop_i; end // PC is taken from hwloop start addr
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`ifdef BRANCH_PREDICTION
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`PC_BRANCH_PRED: begin next_pc = correct_branch; end // take pc from branch prediction
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`PC_BRANCH_PRED: begin next_pc = correct_branch; end // take pc from branch prediction
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`endif
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default: begin next_pc = current_pc_if_o + 32'd4; end
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default: begin next_pc = current_pc_if_o + 32'd4; end
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endcase //~case (pc_mux_sel_i)
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end
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@ -129,33 +129,33 @@ module if_stage
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// NOP = addi x0, x0, 0
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assign instr_rdata_int = (force_nop_i == 1'b1) ? { {25 {1'b0}}, `OPCODE_OPIMM } : instr_rdata_i;
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// IF PC register //
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin : IF_PIPELINE
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if (rst_n == 1'b0)
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begin : ASSERT_RESET
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current_pc_if_o <= 32'h0;
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end
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else
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begin : DEASSERT_RESET
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if ( pc_mux_boot_i == 1'b1 )
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begin
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// set PC to boot address if we were just reset
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current_pc_if_o <= boot_addr_i;
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end
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else if ( dbg_set_npc == 1'b1 )
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begin
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// debug units sets NPC, PC_MUX_SEL holds this value
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current_pc_if_o <= dbg_pc_from_npc;
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end
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else if ( stall_if_i == 1'b0 )
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begin : ENABLED_PIPE
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current_pc_if_o <= next_pc;
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end
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end
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end
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// IF PC register //
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin : IF_PIPELINE
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if (rst_n == 1'b0)
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begin : ASSERT_RESET
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current_pc_if_o <= 32'h0;
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end
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else
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begin : DEASSERT_RESET
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if ( pc_mux_boot_i == 1'b1 )
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begin
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// set PC to boot address if we were just reset
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current_pc_if_o <= boot_addr_i;
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end
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else if ( dbg_set_npc == 1'b1 )
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begin
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// debug units sets NPC, PC_MUX_SEL holds this value
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current_pc_if_o <= dbg_pc_from_npc;
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end
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else if ( stall_if_i == 1'b0 )
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begin : ENABLED_PIPE
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current_pc_if_o <= next_pc;
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end
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end
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end
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`ifdef BRANCH_PREDICTION
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -169,8 +169,8 @@ module if_stage
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end
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else
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begin : DEASSERT_RESET
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if (wrong_branch_taken_i)
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correct_branch <= (take_branch_i) ? branch_taken : branch_not_taken;
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if (wrong_branch_taken_i)
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correct_branch <= (take_branch_i) ? branch_taken : branch_not_taken;
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end
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end
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`endif
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@ -159,13 +159,17 @@
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`define INSTR_MULH { 7'b0000001, {10 {1'b?}}, 3'b001, {5 {1'b?}}, `OPCODE_OP }
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`define INSTR_MULHSU { 7'b0000001, {10 {1'b?}}, 3'b010, {5 {1'b?}}, `OPCODE_OP }
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`define INSTR_MULHU { 7'b0000001, {10 {1'b?}}, 3'b011, {5 {1'b?}}, `OPCODE_OP }
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/*
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/* not implemented
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`define INSTR_DIV { 7'b0000001, {10 {1'b?}}, 3'b100, {5 {1'b?}}, `OPCODE_OP }
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`define INSTR_DIVU { 7'b0000001, {10 {1'b?}}, 3'b101, {5 {1'b?}}, `OPCODE_OP }
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`define INSTR_REM { 7'b0000001, {10 {1'b?}}, 3'b110, {5 {1'b?}}, `OPCODE_OP }
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`define INSTR_REMU { 7'b0000001, {10 {1'b?}}, 3'b111, {5 {1'b?}}, `OPCODE_OP }
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*/
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// Source/Destination register instruction index
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`define REG_RS1 19:15
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`define REG_RS2 24:20
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`define REG_RD 11:07
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//////////////////////////////////////////////////////////////////////////////
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@ -289,10 +293,6 @@
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`define SR_OV 5'd11
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`define SR_DSX 5'd13
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//igor addon
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`define REG_A 20:16
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`define REG_B 15:11
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// forwarding operand mux
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`define SEL_REGFILE 2'b00
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`define SEL_FW_EX 2'b01
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@ -324,7 +324,7 @@
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`define IMM_SB 3'b011
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`define IMM_U 3'b100
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`define IMM_UJ 3'b101
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`define IMM_C4 3'b110
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// PC mux selector defines
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`define INCR_PC 3'b000
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@ -359,7 +359,7 @@ module riscv_core
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.force_nop_o ( force_nop_id ),
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.pc_from_regfile_fw_o ( pc_from_regfile_id ),
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.pc_from_regfile_o ( pc_from_regfile_id ),
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.current_pc_if_i ( current_pc_if ),
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.current_pc_id_i ( current_pc_id ),
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.pc_from_immediate_o ( pc_from_immediate_id ),
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