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Fix Xcelium warnings

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(Likely) fix the following warnings from Xcelium (we cannot actually
confirm that without the tool):

```
                      |fill_ext_req;
                      |
xmvlog: *W,DUPBWO (../src/lowrisc_ibex_ibex_icache_0.1/rtl/ibex_icache.sv,830|22): error prone bit-wise OR ('|') sequence detected [4.1.11(IEEE)].
  `ASSERT_IF(BranchInsTypeOneHot, $onehot0({instr_j, instr_b, instr_cj, instr_cb}), fetch_valid_i);
                                                                                                  |
xmvlog: *W,UEXPSC (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_branch_predict.sv,91|98): Ignored unexpected semicolon following SystemVerilog description keyword (end).
    `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken);
                                                                        |
xmvlog: *W,UEXPSC (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_if_stage.sv,488|72): Ignored unexpected semicolon following SystemVerilog description keyword (end).
    `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn);
                                                                       |
xmvlog: *W,UEXPSC (../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_if_stage.sv,489|71): Ignored unexpected semicolon following SystemVerilog description keyword (end).
```
This commit is contained in:
Philipp Wagner 2020-11-18 09:44:11 +00:00 • committed by Philipp Wagner
parent f829915aee
commit 86084b9d3d
3 changed files with 4 additions and 4 deletions
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2
rtl/ibex_branch_predict.sv
View file

@ -88,7 +88,7 @@ module ibex_branch_predict (
endcase
end
`ASSERT_IF(BranchInsTypeOneHot, $onehot0({instr_j, instr_b, instr_cj, instr_cb}), fetch_valid_i);
`ASSERT_IF(BranchInsTypeOneHot, $onehot0({instr_j, instr_b, instr_cj, instr_cb}), fetch_valid_i)
// Determine branch prediction, taken if offset is negative
assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]);

2
rtl/ibex_icache.sv
View file

@ -827,7 +827,7 @@ module ibex_icache #(
///////////////////////
assign instr_req = ((SpecRequest | branch_i) & lookup_grant_ic0) |
|fill_ext_req;
(|fill_ext_req);
assign instr_addr = |fill_ext_req ? fill_ext_req_addr :
lookup_addr_ic0[ADDR_W-1:BUS_W];

4
rtl/ibex_if_stage.sv
View file

@ -485,8 +485,8 @@ module ibex_if_stage #(
assign instr_bp_taken_o = instr_bp_taken_q;
`ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken);
`ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn);
`ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken)
`ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn)
end else begin : g_no_branch_predictor
assign instr_bp_taken_o = 1'b0;
assign predict_branch_taken = 1'b0;