github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-24 13:57:19 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix syntax in python script

Browse source
This commit is contained in:
Markus Wegmann 2017-01-02 00:30:53 +01:00
parent 5794d5a68d
commit 87c4f51f2a
2 changed files with 24 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

28
include/riscv_config.sv
View file

@ -44,42 +44,42 @@
// CONFIG: MUL_SUPPORT // CONFIG: MUL_SUPPORT
// will enable RISCV32M support for multiplication, division, MAC operations. Uses a lot of multiplications // will enable RISCV32M support for multiplication, division, MAC operations. Uses a lot of multiplications
`define MUL_SUPPORT //`define MUL_SUPPORT
// CONFIG: VEC_SUPPORT // CONFIG: VEC_SUPPORT
// will enable RISCV32V support for vector operations. // will enable RISCV32V support for vector operations.
`define VEC_SUPPORT //`define VEC_SUPPORT
// CONFIG: HWLP_SUPPORT // CONFIG: HWLP_SUPPORT
// will enable hardware loop support. // will enable hardware loop support.
`define HWLP_SUPPORT //`define HWLP_SUPPORT
// CONFIG: BIT_SUPPORT // CONFIG: BIT_SUPPORT
// will enable bit manipulation and counting support. // will enable bit manipulation and counting support.
`define BIT_SUPPORT //`define BIT_SUPPORT
// CONFIG: MATH_SPECIAL_SUPPORT
// will enable clip, min and max operations support.
`define MATH_SPECIAL_SUPPORT
// CONFIG: LSU_ADDER_SUPPORT // CONFIG: LSU_ADDER_SUPPORT
// will enable an additional adder in the LSU for better timings. // will enable an additional adder in the LSU for better timings.
`define LSU_ADDER_SUPPORT //`define LSU_ADDER_SUPPORT
`ifdef LSU_ADDER_SUPPORT `ifdef LSU_ADDER_SUPPORT
// CONFIG: PREPOST_SUPPORT // CONFIG: PREPOST_SUPPORT
// will enable pre/post increment load/store support support. // will enable pre/post increment load/store support support.
`define PREPOST_SUPPORT //`define PREPOST_SUPPORT
`endif // LSU_ADDER_SUPPORT `endif // LSU_ADDER_SUPPORT
// CONFIG: MATH_SPECIAL_SUPPORT
// will enable clip, min and max operations support.
//`define MATH_SPECIAL_SUPPORT
// Dependent definitions // Dependent definitions
// CONFIG: THREE_PORT_REG_FILE // CONFIG: THREE_PORT_REG_FILE
// enables 3r2w reg file (rather than 2r1w) // enables 3r2w reg file (rather than 2r1w)
`define THREE_PORT_REG_FILE //`define THREE_PORT_REG_FILE
`ifndef MUL_SUPPORT `ifndef MUL_SUPPORT
@ -91,15 +91,15 @@
// CONFIG: SIMPLE_ALU // CONFIG: SIMPLE_ALU
// will enable simplified ALU for less gates. It does not support vectors, shuffling, nor bit operations. // will enable simplified ALU for less gates. It does not support vectors, shuffling, nor bit operations.
//`define SIMPLE_ALU `define SIMPLE_ALU
// CONFIG: SMALL_IF // CONFIG: SMALL_IF
// will disable large FIFO in IF stage and use a more simple one. // will disable large FIFO in IF stage and use a more simple one.
//`define SMALL_IF `define SMALL_IF
// CONFIG: RV32E // CONFIG: RV32E
// will reduce the register file to 16 words // will reduce the register file to 16 words
//`define RV32E `define RV32E
`endif `endif
`endif `endif

20
scripts/ri5cly-manage.py
View file

@ -126,7 +126,7 @@ def restoreConfig(new_config_path, littleRISCV_path):
def overwriteConfig(new_config_path, littleRISCV_path, backup=True): def overwriteConfig(new_config_path, littleRISCV_path, backup=True):
print("Overwriting current config (include/riscv_config.sv) with new one ({})".format(new_config_path)) print("Overwriting current config (include/riscv_config.sv) with new one ({})".format(new_config_path))
if backup: if backup:
backupConfig(new_config_path, littleRISCV_path): backupConfig(new_config_path, littleRISCV_path)
shutil.copy(os.path.abspath(new_config_path), os.path.abspath(littleRISCV_path + "/include/riscv_config.sv")) # Copy new config to littleRISCV shutil.copy(os.path.abspath(new_config_path), os.path.abspath(littleRISCV_path + "/include/riscv_config.sv")) # Copy new config to littleRISCV
@ -330,16 +330,16 @@ def synthesize(littleRISCV_path):
p.wait() p.wait()
# Get clock of synopsys setup configuration # Get clock of synopsys setup configuration
with open(os.path.abspath(littleRISCV_path+"/../../../synopsys/scripts/setup/setup.tcl"), encoding="utf8") as f: with open(os.path.abspath(littleRISCV_path+"/../../../synopsys/scripts/setup/setup.tcl"), encoding="utf8") as f:
content = f.readlines() content = f.readlines()
clock_p = re.compile("^set\sCLOCK_SLOW\s(\d+);\.*$") clock_p = re.compile("^set\sCLOCK_SLOW\s(\d+);\.*$")
m = clock_p.match() m = clock_p.match()
if m is not None: if m is not None:
clock = str(m.group(1)) clock = str(m.group(1))
else: else:
clock = "undefined" clock = "undefined"
shutil.rmtree(os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock)), ignore_errors=True) shutil.rmtree(os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock)), ignore_errors=True)
shutil.copytree(os.path.abspath(littleRISCV_path + "/../../../synopsys"), os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock))) shutil.copytree(os.path.abspath(littleRISCV_path + "/../../../synopsys"), os.path.abspath(littleRISCV_path + "/scripts/synthesis_results/custom" + "_{}".format(clock)))
@ -362,7 +362,7 @@ def report_specific(config_name, littleRISCV_path):
if m is not None: if m is not None:
clock = m.group(1) clock = m.group(1)
else else:
clock = "undefined" clock = "undefined"
return "{}\t\t{}".format(config_name,area,clock) return "{}\t\t{}".format(config_name,area,clock)