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Run through linter and do some cleanup
This commit is contained in:
Andreas Traber
parent
9858caff47
commit
8fe67b303d
5 changed files with 38 additions and 43 deletions
63
alu.sv
63
alu.sv
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@ -85,11 +85,6 @@ module alu
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`ALU_SUB, `ALU_ABS:
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begin
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case (vector_mode_i)
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default: // VEC_MODE32
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begin
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carry_in[0] = 1'b1;
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end
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`VEC_MODE16:
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begin
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carry_in[0] = 1'b1;
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@ -100,17 +95,17 @@ module alu
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begin
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carry_in = 4'b1111;
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end
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default: // VEC_MODE32
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begin
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carry_in[0] = 1'b1;
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end
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endcase
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end
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default:
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begin
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case (vector_mode_i)
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default: // VEC_MODE32
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begin
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carry_in[0] = 1'b0;
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end
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`VEC_MODE16:
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begin
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carry_in[0] = 1'b0;
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@ -121,6 +116,11 @@ module alu
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begin
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carry_in = 4'b0000;
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end
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default: // VEC_MODE32
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begin
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carry_in[0] = 1'b0;
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end
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endcase
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end
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endcase
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@ -168,11 +168,6 @@ module alu
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always_comb
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begin
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case(vector_mode_i)
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default: // VEC_MODE32
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begin
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shift_amt_left[31: 0] = shift_amt[31: 0];
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end
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`VEC_MODE16:
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begin
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shift_amt_left[15: 0] = shift_amt[31:16];
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@ -186,6 +181,11 @@ module alu
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shift_amt_left[23:16] = shift_amt[15: 8];
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shift_amt_left[31:24] = shift_amt[ 7: 0];
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end
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default: // VEC_MODE32
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begin
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shift_amt_left[31: 0] = shift_amt[31: 0];
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end
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endcase
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end
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@ -197,16 +197,6 @@ module alu
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always_comb
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begin
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case(vector_mode_i)
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default: // VEC_MODE32
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begin
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if(operator_i == `ALU_SRA)
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shift_result = $unsigned( $signed(shift_op_a) >>> shift_amt_int[4:0] );
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else if(operator_i == `ALU_ROR)
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shift_result = {shift_op_a, shift_op_a} >> shift_amt_int[4:0];
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else
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shift_result = shift_op_a >> shift_amt_int[4:0];
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end
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`VEC_MODE16:
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begin
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if(operator_i == `ALU_SRA)
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@ -238,6 +228,16 @@ module alu
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shift_result[ 7: 0] = shift_op_a[ 7: 0] >> shift_amt_int[ 2: 0];
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end
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end
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default: // VEC_MODE32
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begin
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if(operator_i == `ALU_SRA)
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shift_result = $unsigned( $signed(shift_op_a) >>> shift_amt_int[4:0] );
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else if(operator_i == `ALU_ROR)
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shift_result = {shift_op_a, shift_op_a} >> shift_amt_int[4:0];
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else
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shift_result = shift_op_a >> shift_amt_int[4:0];
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end
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endcase; // case (vec_mode_i)
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end
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@ -294,9 +294,9 @@ module alu
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(operator_i == `ALU_ABS))
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begin
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case (vector_mode_i)
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default: cmp_sign_mode[3:0] = 4'b1000;
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`VEC_MODE16: cmp_sign_mode[3:0] = 4'b1010;
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`VEC_MODE8: cmp_sign_mode[3:0] = 4'b1111;
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default: cmp_sign_mode[3:0] = 4'b1000;
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endcase
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end
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end
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@ -322,8 +322,6 @@ module alu
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| (is_equal_vec[1] & (is_greater_vec[0]))))))}};
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case(vector_mode_i)
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default:; // see default assignment
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`VEC_MODE16:
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begin
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is_equal[1:0] = {2{is_equal_vec[0] & is_equal_vec[1]}};
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@ -337,6 +335,8 @@ module alu
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is_equal[3:0] = is_equal_vec[3:0];
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is_greater[3:0] = is_greater_vec[3:0];
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end
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default:; // see default assignment
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endcase
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end
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@ -550,7 +550,10 @@ module alu
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result_o = shift_left_result;
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end
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`ALU_SRL, `ALU_SRA, `ALU_ROR: result_o = shift_result;
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`ALU_SRL, `ALU_SRA, `ALU_ROR: begin
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shift_left = 1'b0;
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result_o = shift_result;
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end
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// Extension Operations
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`ALU_EXTWZ, `ALU_EXTWS: result_o = operand_a_i;
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@ -592,8 +595,6 @@ module alu
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`ALU_CLB: result_o = {26'h0, clb_result};
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`ALU_CNT: result_o = {26'h0, cnt_result};
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`ALU_NOP: ; // Do nothing
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default: ;
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endcase //~case(operator_i)
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end
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@ -84,7 +84,6 @@ module controller
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input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now
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// Exception Controller Signals
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input logic exc_pc_sel_i, // exception execution requested
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input logic pc_valid_i, // is the next_pc currently valid?
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input logic exc_pipe_flush_i, // flush pipeline after exception handling
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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output logic illegal_insn_o, // illegal instruction encountered
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@ -501,7 +500,7 @@ module controller
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// we unstall the if_stage if the debug unit wants to set a new
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// pc, so that the new value gets written into current_pc_if and is
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// used by the instr_core_interface
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stall_if_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_if | (~pc_valid_i) | (jump_in_id_i == `BRANCH_COND);
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stall_if_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_if | (jump_in_id_i == `BRANCH_COND);
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stall_id_o = instr_ack_stall | load_stall | jr_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | misalign_stall | halt_id;
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stall_ex_o = instr_ack_stall | (~lsu_ready_ex_i) | (~lsu_ready_wb_i) | dbg_stall_i;
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stall_wb_o = (~lsu_ready_wb_i) | dbg_stall_i;
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@ -56,7 +56,6 @@ module exc_controller
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input logic illegal_insn_i, // Illegal instruction encountered in ID stage
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input logic trap_insn_i, // Trap instruction encountered in ID stage
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input logic drop_instruction_i, // If branch prediction went wrong
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output logic pc_valid_o, // is the PC in the IF stage currently valid?
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input logic clear_isr_running_i, // exit ISR routine
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output logic exc_pipe_flush_o, // flush pipeline and go back to sleep
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@ -155,7 +154,6 @@ module exc_controller
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exc_running_n = exc_running_p;
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save_pc_if_o = 1'b0;
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save_pc_id_o = 1'b0;
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pc_valid_o = 1'b1;
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exc_pc_sel_o = 1'b0;
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exc_pc_mux_o = `EXC_PC_NO_INCR;
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@ -189,7 +189,6 @@ module id_stage
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// Signals running between controller and exception controller
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logic illegal_insn;
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logic trap_hit;
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logic pc_valid;
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logic clear_isr_running;
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logic exc_pipe_flush;
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@ -659,7 +658,6 @@ module id_stage
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// Exception Controller Signals
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.exc_pc_sel_i ( exc_pc_sel ),
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.pc_valid_i ( pc_valid ),
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.exc_pipe_flush_i ( exc_pipe_flush ),
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.trap_hit_i ( trap_hit ),
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.illegal_insn_o ( illegal_insn ),
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@ -740,7 +738,6 @@ module id_stage
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.illegal_insn_i ( illegal_insn ),
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.trap_insn_i ( trap_insn ),
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.drop_instruction_i ( 1'b0 ),
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.pc_valid_o ( pc_valid ),
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.clear_isr_running_i ( clear_isr_running ),
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.trap_hit_o ( trap_hit ),
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.exc_pipe_flush_o ( exc_pipe_flush ),
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10
mult.sv
10
mult.sv
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@ -82,11 +82,6 @@ module mult
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always_comb
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begin
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case(vector_mode_i)
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default: // VEC_MODE32, VEC_MODE216
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begin
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result[31: 0] = mac_int + op_a_sel * op_b_sel;
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end
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`VEC_MODE16:
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begin
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result[15: 0] = mac_int[15: 0] + op_a_sel[15: 0] * op_b_sel[15: 0];
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@ -100,6 +95,11 @@ module mult
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result[23:16] = mac_int[23:16] + op_a_sel[23:16] * op_b_sel[23:16];
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result[31:24] = mac_int[31:24] + op_a_sel[31:24] * op_b_sel[31:24];
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end
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default: // VEC_MODE32, VEC_MODE216
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begin
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result[31: 0] = mac_int + op_a_sel * op_b_sel;
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end
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endcase; // case (vec_mode_i)
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end
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