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This fixes the instruction fetch miss performance counter
This commit is contained in:
Andreas Traber
parent
072cd65e65
commit
9ceeb15bc8
6 changed files with 22 additions and 29 deletions
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@ -56,7 +56,6 @@ module controller
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// from prefetcher
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output logic instr_req_o, // Start fetching instructions
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input logic instr_ack_i, // Acknow from instr memory or cache (means that data is available)
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// to prefetcher
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output logic pc_set_o, // jump to address set by pc_mux_sel
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@ -222,7 +221,7 @@ module controller
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FIRST_FETCH:
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begin
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// Stall because of IF miss
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if ((instr_ack_i == 1'b1) && (dbg_stall_i == 1'b0))
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if ((id_valid_i == 1'b1) && (dbg_stall_i == 1'b0))
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begin
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ctrl_fsm_ns = DECODE;
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end
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@ -58,8 +58,7 @@ module cs_registers
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input logic is_compressed_i, // compressed instruction in ID
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input logic is_decoding_i, // controller is in DECODE state
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input logic instr_fetch_i, // instruction fetch
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input logic imiss_i, // instruction fetch
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input logic jump_i, // jump instruction seen (j, jr, jal, jalr)
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input logic branch_i, // branch instruction seen (bf, bnf)
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input logic ld_stall_i, // load use hazard
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@ -228,15 +227,15 @@ module cs_registers
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/////////////////////////////////////////////////////////////////
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assign PCCR_in[0] = 1'b1; // cycle counter
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assign PCCR_in[1] = id_valid_q & is_decoding_i; // instruction counter
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assign PCCR_in[1] = id_valid_i & is_decoding_i; // instruction counter
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assign PCCR_in[2] = ld_stall_i & id_valid_q; // nr of load use hazards
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assign PCCR_in[3] = jr_stall_i & id_valid_q; // nr of jump register hazards
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assign PCCR_in[4] = instr_fetch_i; // cycles waiting for instruction fetches
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assign PCCR_in[4] = imiss_i; // cycles waiting for instruction fetches
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assign PCCR_in[5] = mem_load_i; // nr of loads
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assign PCCR_in[6] = mem_store_i; // nr of stores
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assign PCCR_in[7] = jump_i & id_valid_q; // nr of jumps (unconditional)
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assign PCCR_in[8] = branch_i & id_valid_q; // nr of branches (conditional)
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assign PCCR_in[9] = id_valid_q & is_decoding_i & is_compressed_i; // compressed instruction counter
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assign PCCR_in[9] = id_valid_i & is_decoding_i & is_compressed_i; // compressed instruction counter
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// assign external performance counters
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generate
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@ -45,7 +45,6 @@ module id_stage
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// Interface to instruction memory
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input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage
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output logic instr_req_o,
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input logic instr_ack_i,
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// Jumps and branches
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output logic [1:0] jump_in_id_o,
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@ -636,7 +635,6 @@ module id_stage
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// from prefetcher
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.instr_req_o ( instr_req_o ),
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.instr_ack_i ( instr_ack_i ),
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// to prefetcher
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.pc_set_o ( pc_set_o ),
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22
if_stage.sv
22
if_stage.sv
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@ -46,7 +46,6 @@ module if_stage
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// instruction request control
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input logic req_i,
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output logic valid_o,
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// instruction cache interface
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output logic instr_req_o,
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@ -89,7 +88,8 @@ module if_stage
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output logic if_valid_o,
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// misc signals
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output logic if_busy_o // is the IF stage busy fetching instructions?
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output logic if_busy_o, // is the IF stage busy fetching instructions?
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output logic perf_imiss_o // Instruction Fetch Miss
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);
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// offset FSM
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@ -100,6 +100,8 @@ module if_stage
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logic unaligned;
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logic unaligned_jump;
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logic valid;
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// prefetch buffer related signals
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logic prefetch_busy;
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logic branch_req, branch_req_Q;
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@ -271,7 +273,7 @@ module if_stage
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fetch_ready = 1'b0;
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branch_req = 1'b0;
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valid_o = 1'b0;
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valid = 1'b0;
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unaligned = 1'b0;
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@ -288,7 +290,7 @@ module if_stage
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// serving aligned 32 bit or 16 bit instruction, we don't know yet
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WAIT_ALIGNED: begin
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if (fetch_valid) begin
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valid_o = 1'b1; // an instruction is ready for ID stage
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid_o) begin
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@ -313,7 +315,7 @@ module if_stage
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if (fetch_valid) begin
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if (is_compressed[1]) begin
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valid_o = 1'b1; // an instruction is ready for ID stage
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid_o) begin
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// next instruction will be aligned
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@ -324,7 +326,7 @@ module if_stage
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// not compressed, we are looking at a 32 bit instruction
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if (fetch_unaligned_valid) begin
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valid_o = 1'b1; // an instruction is ready for ID stage
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid_o) begin
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// next instruction will be unaligned
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@ -347,7 +349,7 @@ module if_stage
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if (branch_req_Q == 1'b0) begin
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if (jump_in_ex_i == `BRANCH_COND) begin
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if (branch_decision_i) begin
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valid_o = 1'b0;
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valid = 1'b0;
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// branch taken
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branch_req = 1'b1;
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if (unaligned_jump)
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@ -359,7 +361,7 @@ module if_stage
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end else if (jump_in_id_i == `BRANCH_JAL || jump_in_id_i == `BRANCH_JALR
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|| pc_set_i
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|| hwloop_jump_i) begin
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valid_o = 1'b0;
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valid = 1'b0;
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// switch to new PC from ID stage
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branch_req = 1'b1;
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@ -374,6 +376,8 @@ module if_stage
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assign if_busy_o = prefetch_busy;
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assign perf_imiss_o = (~fetch_valid) | branch_req;
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// compressed instruction decoding, or more precisely compressed instruction
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// expander
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@ -415,7 +419,7 @@ module if_stage
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end
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end
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assign if_ready_o = valid_o & id_ready_i;
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assign if_ready_o = valid & id_ready_i;
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assign if_valid_o = (~halt_if_i) & if_ready_o & (jump_in_id_i != `BRANCH_COND);
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endmodule
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@ -65,11 +65,6 @@ module prefetch_L0_buffer
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logic valid_previous_chunk;
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logic clear_buffer;
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logic [15:0] L0_buffer_misaligned;
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assign L0_buffer_misaligned[15:0] = previous_chunk;
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assign busy_o = (CS != EMPTY);
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@ -178,7 +178,6 @@ module riscv_core
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// Signals between instruction core interface and pipe (if and id stages)
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logic instr_req_int; // Id stage asserts a req to instruction core interface
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logic instr_ack_int; // instr core interface acks the request now (read data is available)
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// Interrupts
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logic irq_enable;
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@ -211,6 +210,7 @@ module riscv_core
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logic dbg_set_npc;
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// Performance Counters
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logic perf_imiss;
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logic perf_jump;
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logic perf_branch;
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logic perf_jr_stall;
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@ -242,7 +242,6 @@ module riscv_core
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// instruction request control
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.req_i ( instr_req_int ),
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.valid_o ( instr_ack_int ),
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// instruction cache interface
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.instr_req_o ( instr_req_o ),
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@ -284,7 +283,8 @@ module riscv_core
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.id_ready_i ( id_ready ),
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.if_valid_o ( if_valid ),
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.if_busy_o ( if_busy )
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.if_busy_o ( if_busy ),
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.perf_imiss_o ( perf_imiss )
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);
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@ -309,7 +309,6 @@ module riscv_core
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// Interface to instruction memory
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.instr_rdata_i ( instr_rdata_id ),
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.instr_req_o ( instr_req_int ),
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.instr_ack_i ( instr_ack_int ),
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// Jumps and branches
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.jump_in_id_o ( jump_in_id ),
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@ -573,8 +572,7 @@ module riscv_core
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.is_compressed_i ( is_compressed_id ),
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.is_decoding_i ( is_decoding ),
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.instr_fetch_i ( ~instr_ack_int ),
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.imiss_i ( perf_imiss ),
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.jump_i ( perf_jump ),
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.branch_i ( perf_branch ),
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.ld_stall_i ( perf_ld_stall ),
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