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https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
Move stall and IF-ID control from ID stage into controller
This commit is contained in:
Pirmin Vogel
parent
3eb147dbc2
commit
a6c2846346
4 changed files with 73 additions and 62 deletions
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@ -44,16 +44,19 @@ module ibex_controller (
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input logic ebrk_insn_i, // decoder has EBREAK instr
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input logic csr_status_i, // decoder has CSR status instr
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// from IF/ID pipeline
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// from IF-ID pipeline stage
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input logic instr_valid_i, // instr from IF-ID reg is valid
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input logic [31:0] instr_i, // instr from IF-ID reg, for mtval
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input logic [15:0] instr_compressed_i, // instr from IF-ID reg, for mtval
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input logic instr_is_compressed_i, // instr from IF-ID reg is compressed
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// from prefetcher
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output logic instr_req_o, // start fetching instructions
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// to IF-ID pipeline stage
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_ready_o, // ID stage is ready for new instr
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output logic halt_if_o, // request halt of IF stage
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// to prefetcher
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output logic instr_req_o, // start fetching instructions
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output logic pc_set_o, // jump to address set by pc_mux
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output ibex_defines::pc_sel_e pc_mux_o, // IF stage fetch address selector
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// (boot, normal, exception...)
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@ -69,8 +72,6 @@ module ibex_controller (
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input logic branch_set_i, // branch taken set signal
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input logic jump_set_i, // jump taken set signal
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input logic instr_multicyle_i, // multicycle instructions active
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// External Interrupt Req Signals, used to wake up from wfi even if the interrupt is not taken
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input logic irq_i,
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// Interrupt Controller Signals
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@ -101,16 +102,19 @@ module ibex_controller (
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output logic [31:0] csr_mtval_o,
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// stall signals
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output logic halt_if_o,
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output logic halt_id_o,
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input logic stall_lsu_i,
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input logic stall_multdiv_i,
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input logic stall_jump_i,
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input logic stall_branch_i,
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input logic instr_multicyle_i, // multicycle instructions active
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input logic id_ready_i, // ID stage is ready
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output logic id_valid_o,
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump
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// instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch
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// instruction
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output logic perf_jump_o, // we are executing a jump
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// instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch
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// instruction
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);
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import ibex_defines::*;
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@ -128,6 +132,8 @@ module ibex_controller (
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logic load_err_q, load_err_n;
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logic store_err_q, store_err_n;
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logic halt_id;
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`ifndef SYNTHESIS
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// synopsys translate_off
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// make sure we are called later so that we do not generate messages for
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@ -174,7 +180,7 @@ module ibex_controller (
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first_fetch_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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halt_id = 1'b0;
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irq_ack_o = 1'b0;
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irq_id_o = irq_id_ctrl_i;
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irq_enable_int = m_IE_i;
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@ -213,7 +219,7 @@ module ibex_controller (
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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ctrl_fsm_ns = SLEEP;
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end
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@ -224,7 +230,7 @@ module ibex_controller (
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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// normal execution flow
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// in debug mode or single step mode we leave immediately (wfi=nop)
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@ -236,7 +242,7 @@ module ibex_controller (
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FIRST_FETCH: begin
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first_fetch_o = 1'b1;
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// Stall because of IF miss
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if (id_ready_i) begin
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if (id_ready_o) begin
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ctrl_fsm_ns = DECODE;
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end
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@ -246,14 +252,14 @@ module ibex_controller (
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// going to sleep.
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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end
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// enter debug mode
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if (debug_req_i && !debug_mode_q) begin
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ctrl_fsm_ns = DBG_TAKEN_IF;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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end
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end
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@ -272,14 +278,14 @@ module ibex_controller (
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// Enter debug mode from external request
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ctrl_fsm_ns = DBG_TAKEN_ID;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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end
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irq_req_ctrl_i && irq_enable_int && !debug_req_i && !debug_mode_q: begin
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// Serve an interrupt (not in debug mode)
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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end
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default: begin
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@ -300,7 +306,7 @@ module ibex_controller (
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store_err_i || load_err_i) begin
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ctrl_fsm_ns = FLUSH;
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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load_err_n = load_err_i;
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store_err_n = store_err_i;
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end
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@ -399,7 +405,7 @@ module ibex_controller (
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FLUSH: begin
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halt_if_o = 1'b1;
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halt_id_o = 1'b1;
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halt_id = 1'b1;
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if (!pipe_flush_i) begin
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ctrl_fsm_ns = DECODE;
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@ -519,6 +525,15 @@ module ibex_controller (
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// instruction
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assign deassert_we_o = ~is_decoding_o | illegal_insn_i;
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// signal to IF stage that ID stage is ready for next instruction
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assign id_ready_o = ~stall_lsu_i & ~stall_multdiv_i & ~stall_jump_i & ~stall_branch_i;
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// kill instruction in IF-ID reg for instructions that are done
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assign instr_valid_clear_o = id_ready_o | halt_id;
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// signal that ID stage has valid output
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assign id_valid_o = id_ready_o & ~halt_id;
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// update registers
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always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
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if (!rst_ni) begin
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@ -117,7 +117,7 @@ module ibex_core #(
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logic [31:0] pc_if; // Program counter in IF stage
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logic [31:0] pc_id; // Program counter in ID stage
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logic clear_instr_valid;
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logic instr_valid_clear;
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logic pc_set;
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pc_sel_e pc_mux_id; // Mux selector for next PC
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exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC
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@ -321,7 +321,7 @@ module ibex_core #(
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.pc_id_o ( pc_id ),
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// control signals
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.clear_instr_valid_i ( clear_instr_valid ),
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.instr_valid_clear_i ( instr_valid_clear ),
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.pc_set_i ( pc_set ),
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.pc_mux_i ( pc_mux_id ),
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.exc_pc_mux_i ( exc_pc_mux_id ),
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@ -376,7 +376,7 @@ module ibex_core #(
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.branch_decision_i ( branch_decision ),
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// IF and ID control signals
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.clear_instr_valid_o ( clear_instr_valid ),
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.instr_valid_clear_o ( instr_valid_clear ),
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.pc_set_o ( pc_set ),
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.pc_mux_o ( pc_mux_id ),
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.exc_pc_mux_o ( exc_pc_mux_id ),
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@ -57,12 +57,14 @@ module ibex_id_stage #(
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input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
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input logic instr_is_compressed_i,
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output logic instr_req_o,
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_ready_o, // ID stage is ready for next instr
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output logic halt_if_o, // ID stage requests IF stage to halt
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// Jumps and branches
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input logic branch_decision_i,
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// IF and ID stage signals
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output logic clear_instr_valid_o,
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output logic pc_set_o,
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output ibex_defines::pc_sel_e pc_mux_o,
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output ibex_defines::exc_pc_sel_e exc_pc_mux_o,
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@ -72,8 +74,6 @@ module ibex_id_stage #(
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input logic [31:0] pc_id_i,
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// Stalls
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output logic halt_if_o, // controller requests a halt of the IF stage
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output logic id_ready_o, // ID stage is ready for the next instruction
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input logic ex_ready_i,
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output logic id_valid_o, // ID stage is done
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@ -174,13 +174,11 @@ module ibex_id_stage #(
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logic jump_in_id, jump_in_dec;
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logic instr_multicyle;
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logic load_stall;
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logic multdiv_stall;
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logic branch_stall;
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logic jump_stall;
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logic stall_lsu;
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logic stall_multdiv;
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logic stall_branch;
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logic stall_jump;
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logic halt_id;
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//FSM signals to write back multi cycles instructions
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logic regfile_we;
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typedef enum logic {RF_LSU, RF_EX} select_e;
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@ -276,10 +274,6 @@ module ibex_id_stage #(
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//else
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assign illegal_reg_rv32e = 1'b0;
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// kill instruction in the IF/ID stage by setting the instr_valid_id control
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// signal to 0 for instructions that are done
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assign clear_instr_valid_o = id_ready_o | halt_id;
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/////////////
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// LSU Mux //
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/////////////
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@ -479,12 +473,17 @@ module ibex_id_stage #(
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.ebrk_insn_i ( ebrk_insn ),
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.csr_status_i ( csr_status ),
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// from IF/ID pipeline
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// from IF-ID pipeline
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.instr_valid_i ( instr_valid_i ),
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.instr_i ( instr ),
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.instr_compressed_i ( instr_rdata_c_i ),
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.instr_is_compressed_i ( instr_is_compressed_i ),
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// to IF-ID pipeline
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.instr_valid_clear_o ( instr_valid_clear_o ),
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.id_ready_o ( id_ready_o ),
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.halt_if_o ( halt_if_o ),
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// from prefetcher
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.instr_req_o ( instr_req_o ),
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@ -533,11 +532,13 @@ module ibex_id_stage #(
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.debug_single_step_i ( debug_single_step_i ),
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.debug_ebreakm_i ( debug_ebreakm_i ),
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// Stall signals
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.halt_if_o ( halt_if_o ),
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.halt_id_o ( halt_id ),
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// stall signals
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.stall_lsu_i ( stall_lsu ),
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.stall_multdiv_i ( stall_multdiv ),
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.stall_jump_i ( stall_jump ),
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.stall_branch_i ( stall_branch ),
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.id_ready_i ( id_ready_o ),
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.id_valid_o ( id_valid_o ),
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// Performance Counters
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.perf_jump_o ( perf_jump_o ),
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@ -626,10 +627,10 @@ module ibex_id_stage #(
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always_comb begin : id_wb_fsm
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id_wb_fsm_ns = id_wb_fsm_cs;
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regfile_we = regfile_we_id;
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load_stall = 1'b0;
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multdiv_stall = 1'b0;
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jump_stall = 1'b0;
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branch_stall = 1'b0;
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stall_lsu = 1'b0;
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stall_multdiv = 1'b0;
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stall_jump = 1'b0;
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stall_branch = 1'b0;
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select_data_rf = RF_EX;
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instr_multicyle = 1'b0;
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branch_set_n = 1'b0;
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@ -648,13 +649,13 @@ module ibex_id_stage #(
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//LSU operation
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regfile_we = 1'b0;
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id_wb_fsm_ns = WAIT_MULTICYCLE;
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load_stall = 1'b1;
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stall_lsu = 1'b1;
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instr_multicyle = 1'b1;
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end
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branch_in_id: begin
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//Cond Branch operation
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id_wb_fsm_ns = branch_decision_i ? WAIT_MULTICYCLE : IDLE;
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branch_stall = branch_decision_i;
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stall_branch = branch_decision_i;
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instr_multicyle = branch_decision_i;
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branch_set_n = branch_decision_i;
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perf_branch_o = 1'b1;
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@ -663,14 +664,14 @@ module ibex_id_stage #(
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//MUL or DIV operation
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regfile_we = 1'b0;
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id_wb_fsm_ns = WAIT_MULTICYCLE;
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multdiv_stall = 1'b1;
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stall_multdiv = 1'b1;
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instr_multicyle = 1'b1;
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end
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jump_in_id: begin
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//UnCond Branch operation
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regfile_we = 1'b0;
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id_wb_fsm_ns = WAIT_MULTICYCLE;
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jump_stall = 1'b1;
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stall_jump = 1'b1;
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instr_multicyle = 1'b1;
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jump_set = 1'b1;
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end
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@ -682,17 +683,17 @@ module ibex_id_stage #(
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if (ex_ready_i) begin
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regfile_we = regfile_we_id;
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id_wb_fsm_ns = IDLE;
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load_stall = 1'b0;
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multdiv_stall = 1'b0;
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stall_lsu = 1'b0;
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stall_multdiv = 1'b0;
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select_data_rf = data_req_id ? RF_LSU : RF_EX;
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end else begin
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regfile_we = 1'b0;
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instr_multicyle = 1'b1;
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unique case (1'b1)
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data_req_id:
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load_stall = 1'b1;
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stall_lsu = 1'b1;
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multdiv_en_id:
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multdiv_stall = 1'b1;
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stall_multdiv = 1'b1;
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default:;
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endcase
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end
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@ -702,11 +703,6 @@ module ibex_id_stage #(
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endcase
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end
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// stall control
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assign id_ready_o = ~load_stall & ~branch_stall & ~jump_stall & ~multdiv_stall;
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assign id_valid_o = ~halt_id & id_ready_o;
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////////////////
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// Assertions //
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////////////////
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@ -61,7 +61,7 @@ module ibex_if_stage #(
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output logic [31:0] pc_id_o,
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// Forwarding ports - control signals
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input logic clear_instr_valid_i, // clear instr valid bit in IF-ID
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input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
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input logic pc_set_i, // set the PC to a new value
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input logic [31:0] csr_mepc_i, // PC to restore after handling
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// the interrupt/exception
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@ -246,7 +246,7 @@ module ibex_if_stage #(
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instr_is_compressed_id_o <= instr_is_compressed_int;
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illegal_c_insn_id_o <= illegal_c_insn;
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pc_id_o <= pc_if_o;
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end else if (clear_instr_valid_i) begin
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end else if (instr_valid_clear_i) begin
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instr_valid_id_o <= 1'b0;
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end
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end
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