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Make sure performance counters work correctly on FPGA

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This commit is contained in:
Andreas Traber 2015-12-15 13:57:26 +01:00
parent d84ae50481
commit a6c4f6d4ef
1 changed files with 8 additions and 7 deletions
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15
cs_registers.sv
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@ -25,6 +25,11 @@
`include "riscv_defines.sv"
`ifndef PULP_FPGA_EMUL
`ifdef SYNTHESIS
`define ASIC_SYNTHESIS
`endif
`endif
module riscv_cs_registers
#(
@ -86,9 +91,7 @@ module riscv_cs_registers
localparam N_PERF_COUNTERS = 10 + N_EXT_CNT;
`ifdef PULP_FPGA_EMUL
localparam N_PERF_REGS = N_PERF_COUNTERS;
`elsif SYNTHESIS
`ifdef ASIC_SYNTHESIS
localparam N_PERF_REGS = 1;
`else
localparam N_PERF_REGS = N_PERF_COUNTERS;
@ -322,9 +325,7 @@ module riscv_cs_registers
is_pccr = 1'b1;
pccr_index = csr_addr_i[4:0];
`ifndef PULP_FPGA_EMUL
perf_rdata = PCCR_q[csr_addr_i[4:0]];
`elsif SYNTHESIS
`ifdef ASIC_SYNTHESIS
perf_rdata = PCCR_q[0];
`else
perf_rdata = PCCR_q[csr_addr_i[4:0]];
@ -335,7 +336,7 @@ module riscv_cs_registers
// performance counter counter update logic
`ifdef SYNTHESIS
`ifdef ASIC_SYNTHESIS
// for synthesis we just have one performance counter register
assign PCCR_inc[0] = (|(PCCR_in & PCER_q)) & PCMR_q[0];