github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 04:47:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Clean headers

Browse source
This commit is contained in:
Andreas Traber 2015-12-14 16:39:16 +01:00
parent 4b9fc6af99
commit d84ae50481
19 changed files with 68 additions and 57 deletions
Download patch file Download diff file Expand all files Collapse all files

1
alu.sv
View file

@ -15,6 +15,7 @@
// Igor Loi - igor.loi@unibo.it //
// Andreas Traber - atraber@student.ethz.ch //
// //
// Design Name: ALU //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

3
compressed_decoder.sv
View file

@ -11,9 +11,6 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Sven Stucki - svstucki@student.ethz.ch //
// //
// Additional contributions by: //
// //
// //
// Design Name: Compressed instruction decoder //
// Project Name: RI5CY //
// Language: SystemVerilog //

28
controller.sv
View file

@ -1,6 +1,14 @@
// Copyright 2015 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
////////////////////////////////////////////////////////////////////////////////
// Company: IIS @ ETHZ - Federal Institute of Technology //
// //
// Engineer: Matthias Baer - baermatt@student.ethz.ch //
// //
// Additional contributions by: //
@ -8,26 +16,12 @@
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Create Date: 19/09/2013 //
// Design Name: RISC-V processor core //
// Module Name: controller.sv //
// Design Name: Main controller //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Main CPU controller of the processor //
// //
// //
// Revision: //
// Revision v0.1 - File Created //
// Revision v0.2 - (August 8th 2014) Changed port and signal names, added //
// comments //
// Revision v0.3 - (December 1th 2014) Merged debug unit //
// Revision v0.4 - (January 6th 2015) Added vectorial instructions //
// Revision v0.5 - (Sept 15th 2015) Separated controller and decoder //
// //
// //
// //
////////////////////////////////////////////////////////////////////////////////
`include "riscv_defines.sv"

3
cs_registers.sv
View file

@ -12,8 +12,9 @@
// Engineer: Sven Stucki - svstucki@student.ethz.ch //
// //
// Additional contributions by: //
// Andreas Traber - atraber@iis.ee.ethz.ch //
// //
// //
// Design Name: Control and Status Registers //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

2
debug_unit.sv
View file

@ -15,7 +15,7 @@
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: Debug Unit //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

2
decoder.sv
View file

@ -16,7 +16,7 @@
// Igor Loi - igor.loi@unibo.it //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: Decoder //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

1
ex_stage.sv
View file

@ -15,7 +15,6 @@
// Igor Loi - igor.loi@unibo.it //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: Excecute stage //
// Project Name: RI5CY //
// Language: SystemVerilog //

2
exc_controller.sv
View file

@ -14,7 +14,7 @@
// Additional contributions by: //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: Exception Controller //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

3
hwloop_controller.sv
View file

@ -11,9 +11,6 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch //
// //
// Additional contributions by: //
// //
// //
// Design Name: hwloop controller //
// Project Name: RI5CY //
// Language: SystemVerilog //

3
hwloop_regs.sv
View file

@ -11,9 +11,6 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch //
// //
// Additional contributions by: //
// //
// //
// Design Name: hwloop regs //
// Project Name: RI5CY //
// Language: SystemVerilog //

3
id_stage.sv
View file

@ -16,8 +16,7 @@
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: Decode stage //
// Design Name: Instruction Decode Stage //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

3
if_stage.sv
View file

@ -16,8 +16,7 @@
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Design Name: RISC-V processor core //
// Design Name: Instruction Fetch Stage //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

1
load_store_unit.sv
View file

@ -14,7 +14,6 @@
// Additional contributions by: //
// Andreas Traber - atraber@iis.ee.ethz.ch //
// //
// //
// Design Name: Load Store Unit //
// Project Name: RI5CY //
// Language: SystemVerilog //

3
mult.sv
View file

@ -14,8 +14,7 @@
// Additional contributions by: //
// Andreas Traber - atraber@student.ethz.ch //
// //
// //
// Design Name: Vectorial Multiplier and MAC //
// Design Name: Subword multiplier and MAC //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

6
prefetch_L0_buffer.sv
View file

@ -9,12 +9,12 @@
// specific language governing permissions and limitations under the License.
////////////////////////////////////////////////////////////////////////////////
// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
// Engineer: Igor Loi - igor.loi@unibo.it //
// //
// Additional contributions by: //
// Andreas Traber - atraber@iis.ee.ethz.ch //
// //
// //
// Design Name: RISC-V processor core //
// Design Name: Prefetcher Buffer for 128 bit memory interface //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

5
prefetch_buffer.sv
View file

@ -11,10 +11,7 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
// //
// Additional contributions by: //
// //
// //
// Design Name: RISC-V processor core //
// Design Name: Prefetcher Buffer for 32 bit memory interface //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //

16
register_file.sv
View file

@ -8,6 +8,22 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
////////////////////////////////////////////////////////////////////////////////
// Engineer: Antonio Pullini - pullinia@iis.ee.ethz.ch //
// //
// Additional contributions by: //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// Design Name: RISC-V register file //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Register file with 31x 32 bit wide registers. Register 0 //
// is fixed to 0. This register file is based on latches and //
// is thus smaller than the flip-flop based register file. //
// //
////////////////////////////////////////////////////////////////////////////////
module riscv_register_file
#(
parameter ADDR_WIDTH = 5,

23
register_file_ff.sv
View file

@ -8,18 +8,17 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/******************************************************************************
* *
* ERC Multitherman Lab @ DEI - University of Bologna *
* Viale Pepoli 3/2 - 40136 *
* Bologna - phone 0512092759 *
* *
* Engineer: Francesco Conti - f.conti@unibo.it *
* *
* Project: PULP FPGA emulator *
* Description: Triple-port behavioral register file *
* *
******************************************************************************/
////////////////////////////////////////////////////////////////////////////////
// Engineer: Francesco Conti - f.conti@unibo.it //
// //
// Design Name: RISC-V register file //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Register file with 31x 32 bit wide registers. Register 0 //
// is fixed to 0. This register file is based on flip-flops. //
// //
////////////////////////////////////////////////////////////////////////////////
module riscv_register_file
#(

17
riscv_core.sv
View file

@ -8,6 +8,23 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
////////////////////////////////////////////////////////////////////////////////
// Engineer: Matthias Baer - baermatt@student.ethz.ch //
// //
// Additional contributions by: //
// Igor Loi - igor.loi@unibo.it //
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// Design Name: Top level module //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Top level module of the RISC-V core. //
// //
////////////////////////////////////////////////////////////////////////////////
`include "riscv_defines.sv"
module riscv_core