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Fix debug breakpoints (dbg_set_npc)

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Sven Stucki 2015-10-29 14:01:42 +01:00
parent 0fcdbf130f
commit a770811ad4
2 changed files with 3 additions and 1 deletions
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3
if_stage.sv
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@ -84,6 +84,7 @@ module riscv_if_stage
// from debug unit
input logic [31:0] dbg_npc_i,
input logic dbg_set_npc_i,
// pipeline stall
input logic halt_if_i,
@ -350,7 +351,7 @@ module riscv_if_stage
// take care of jumps and branches
// only send one branch request per jump/branch
if (branch_req_Q == 1'b0) begin
if (dbg_set_npc_i || (branch_req_Q == 1'b0)) begin
if (pc_set_i) begin
valid = 1'b0;

1
riscv_core.sv
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@ -274,6 +274,7 @@ module riscv_core
// from debug unit
.dbg_npc_i ( dbg_npc ),
.dbg_set_npc_i ( dbg_set_npc ),
// Jump and branch target and decision
.jump_in_id_i ( jump_in_id ),