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Fixed inferred latches in RV

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Sven Stucki 2015-06-05 12:23:35 +02:00
parent b9e0bd9cbd
commit aa1821ba2d
2 changed files with 6 additions and 3 deletions
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2
cs_registers.sv
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@ -99,6 +99,7 @@ module cs_registers
// address decoder for constant CSRs
always_comb
begin
constant_rdata_int = '0;
is_constant = 1'b1;
unique case (csr_addr_i)
12'hF00: constant_rdata_int = 32'h00_00_01_00; // mcpuid: RV32I
@ -112,6 +113,7 @@ module cs_registers
// address decoder for regular CSRs
always_comb
begin
csr_index = '0;
is_register = 1'b1;
unique case (csr_addr_i)
12'h340: csr_index = `CSR_IDX_MSCRATCH;

7
wb_stage.sv
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@ -55,9 +55,10 @@ module wb_stage
// 1: From Data Memory
always_comb
begin : REGFILE_WDATA_MUX
casex (regfile_wdata_mux_sel_i)
//1'b0: begin regfile_wdata_o <= sp_rdata_i; end
1'b1: begin regfile_wdata_o <= data_rdata_i; end
case (regfile_wdata_mux_sel_i)
//1'b0: regfile_wdata_o <= sp_rdata_i;
1'b1: regfile_wdata_o <= data_rdata_i;
default: regfile_wdata_o <= data_rdata_i;
endcase; // case (regfile_wdata_mux_sel_i)
end