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Revert "[rtl] Fix counter reset value on FPGA"

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This reverts commit 54985d21b0.
This commit is contained in:
Pascal Nasahl 2024-12-02 16:05:24 +01:00 • committed by GitHub
parent 54985d21b0
commit b30abd4eb2
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1 changed files with 9 additions and 12 deletions
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15
rtl/ibex_counter.sv
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@ -51,17 +51,12 @@ module ibex_counter #(
end end
`ifdef FPGA_XILINX `ifdef FPGA_XILINX
// On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
// counter.
if (CounterWidth < 49) begin : g_dsp_counter
// Set DSP pragma for supported xilinx FPGAs // Set DSP pragma for supported xilinx FPGAs
(* use_dsp = "yes" *) logic [CounterWidth-1:0] counter_q; localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
(* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
// DSP output register requires synchronous reset. // DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i `define COUNTER_FLOP_RST posedge clk_i
end else begin : g_no_dsp_counter
(* use_dsp = "no" *) logic [CounterWidth-1:0] counter_q;
`define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
end
`else `else
logic [CounterWidth-1:0] counter_q; logic [CounterWidth-1:0] counter_q;
@ -70,7 +65,6 @@ module ibex_counter #(
// Counter flop // Counter flop
always_ff @(`COUNTER_FLOP_RST) begin always_ff @(`COUNTER_FLOP_RST) begin
`undef COUNTER_FLOP_RST
if (!rst_ni) begin if (!rst_ni) begin
counter_q <= '0; counter_q <= '0;
end else begin end else begin
@ -104,3 +98,6 @@ module ibex_counter #(
assign counter_val_o = counter; assign counter_val_o = counter;
endmodule endmodule
// Keep helper defines file-local.
`undef COUNTER_FLOP_RST