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Add better dependencies for the coverage targets using stampfiles

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Harry Callahan 2022-04-07 16:19:36 +01:00 • committed by Rupert Swarbrick
parent 9b52fc132a
commit b4eb7323f7
1 changed files with 15 additions and 5 deletions
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20
dv/uvm/core_ibex/Makefile
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@ -111,7 +111,7 @@ all: sim
instr: iss_sim
sim: post_compare $(if $(filter 1,$(COV)),gen_cov,)
sim: post_compare $(if $(filter 1,$(COV)),merge_cov,)
.PHONY: clean
clean:
@ -522,8 +522,7 @@ post_compare: $(OUT-SEED)/regr.log
###############################################################################
# Generate RISCV-DV functional coverage
# TODO(udi) - add B extension
.PHONY: riscv_dv_cov
riscv_dv_fcov: $(rtl-sim-logs)
$(metadata)/.cov.gen_fcov.stamp: $(rtl-sim-logs)
$(verb)python3 ${GEN_DIR}/cov.py \
--core ibex \
--dir ${OUT-SEED}/rtl_sim \
@ -532,14 +531,25 @@ riscv_dv_fcov: $(rtl-sim-logs)
--opts "--gen_timeout 1000" \
--isa rv32imcb \
--custom_target riscv_dv_extension
@ # Bookkeeping
@touch $@
.PHONY: riscv_dv_fcov
riscv_dv_fcov: $(metadata)/.cov.gen_fcov.stamp
###############################################################################
# Merge all output coverage directories into the <out>/rtl_sim directory
#
# Any coverage databases generated from the riscv_dv_fcov target will be merged as well.
.PHONY: gen_cov
gen_cov: riscv_dv_fcov
$(metadata)/.cov.merge.stamp: \
$(metadata)/.cov.gen_fcov.stamp
$(verb)rm -rf $(OUT-DIR)rtl_sim/test.vdb
$(verb)./sim.py --steps=cov --simulator="${SIMULATOR}" $(lsf-arg) --o="$(OUT-DIR)"
@if [ -d "test.vdb" ]; then \
mv -f test.vdb $(OUT-DIR)rtl_sim/; \
fi
@ # Bookkeeping
@touch $@
.PHONY: merge_cov
merge_cov: $(metadata)/.cov.merge.stamp