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Fix linting errors due to default in fully-specified case statements

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This commit replaces fully-specified, binary case statements with default
case by a simple one-line assignment to avoid linting errors. Removing the
default would also work but is more error prone if at a later point more
case are added and the statement is no longer fully-specified.
This commit is contained in:
Pirmin Vogel 2019-05-09 17:22:44 +01:00 • committed by Philipp Wagner
parent c5f32e4737
commit c26d89d15e
1 changed files with 3 additions and 21 deletions
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24
rtl/ibex_id_stage.sv
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@ -228,8 +228,6 @@ module ibex_id_stage #(
logic [31:0] operand_a_fw_id;
logic [31:0] operand_b;
logic [31:0] alu_operand_a;
logic [31:0] alu_operand_b;
@ -245,7 +243,6 @@ module ibex_id_stage #(
// immediate for CSR manipulatin (zero extended)
assign zimm_rs1_type = { 27'b0, instr[`REG_S1] };
///////////////////////////////
// Source register selection //
///////////////////////////////
@ -285,14 +282,8 @@ module ibex_id_stage #(
assign imm_a = (imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : '0;
// Operand a forwarding mux used with LSU instructions
always_comb begin : operand_a_fw_mux
case (operand_a_fw_mux_sel)
SEL_MISALIGNED: operand_a_fw_id = misaligned_addr_i;
SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id;
default: operand_a_fw_id = regfile_data_ra_id;
endcase // case (operand_a_fw_mux_sel)
end
assign operand_a_fw_id
= (operand_a_fw_mux_sel == SEL_MISALIGNED) ? misaligned_addr_i : regfile_data_ra_id;
///////////////
// Operand B //
@ -312,15 +303,7 @@ module ibex_id_stage #(
end
// ALU_Op_b Mux
always_comb begin : alu_operand_b_mux
case (alu_op_b_mux_sel)
OP_B_REGB_OR_FWD: operand_b = regfile_data_rb_id;
OP_B_IMM: operand_b = imm_b;
default: operand_b = regfile_data_rb_id;
endcase // case (alu_op_b_mux_sel)
end
assign alu_operand_b = operand_b;
assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_data_rb_id;
///////////////
// Registers //
@ -656,7 +639,6 @@ module ibex_id_stage #(
assign id_valid_o = ~halt_id & id_ready_o;
////////////////
// Assertions //
////////////////