c26d89d15e
This commit replaces fully-specified, binary case statements with default case by a simple one-line assignment to avoid linting errors. Removing the default would also work but is more error prone if at a later point more case are added and the statement is no longer fully-specified. |
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| doc | ||
| rtl | ||
| .gitignore | ||
| ibex.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
Ibex: RISC-V Core
Ibex is a small 32 bit RISC-V core with a 2-stage pipeline.
Ibex fully implements the RV32IMC instruction set and a small set of RISC-V privileged specifications. Ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions.
This core was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further.
Ibex is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Documentation
The Ibex documentation can be read online at ReadTheDocs.
It is also contained in the doc folder of this repository.
We highly appreciate pull requests on the documentation if you find anything wrong or outdated!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).