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Fix misaligned access, they did not correctly forward and used the wrong

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increment...
This commit is contained in:
Andreas Traber 2015-09-14 12:46:46 +02:00
parent 1b2a80e7c9
commit d2a549bfae
2 changed files with 9 additions and 8 deletions
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15
controller.sv
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@ -919,7 +919,7 @@ module controller
// correct operands are sent to the AGU
alu_op_a_mux_sel_o = `OP_A_REGA_OR_FWD;
alu_op_b_mux_sel_o = `OP_B_IMM;
immediate_mux_sel_o = `IMM_I; // TODO: FIXME
immediate_mux_sel_o = `IMM_PCINCR;
// if prepost increments are used, we do not write back the
// second address since the first calculated address was
@ -1338,17 +1338,18 @@ module controller
operand_c_fw_mux_sel_o = `SEL_FW_EX;
end
if (data_misaligned_i == 1'b1)
begin
operand_a_fw_mux_sel_o = `SEL_FW_EX;
operand_b_fw_mux_sel_o = `SEL_REGFILE;
end
// Make sure x0 is never forwarded
if (instr_rdata_i[`REG_S1] == 5'b0)
operand_a_fw_mux_sel_o = `SEL_REGFILE;
if (instr_rdata_i[`REG_S2] == 5'b0)
operand_b_fw_mux_sel_o = `SEL_REGFILE;
// for misaligned memory accesses
if (data_misaligned_i == 1'b1)
begin
operand_a_fw_mux_sel_o = `SEL_FW_EX;
operand_b_fw_mux_sel_o = `SEL_REGFILE;
end
end
// update registers

2
id_stage.sv
View file

@ -408,7 +408,7 @@ module id_stage
`IMM_I: immediate_b = imm_i_type;
`IMM_S: immediate_b = imm_s_type;
`IMM_U: immediate_b = imm_u_type;
`IMM_PCINCR: immediate_b = is_compressed_i ? 32'h2 : 32'h4;
`IMM_PCINCR: immediate_b = (is_compressed_i && (~data_misaligned_i)) ? 32'h2 : 32'h4;
default: immediate_b = imm_i_type;
endcase; // case (immediate_mux_sel)
end