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docs/datasheet
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Add a basic datasheet for RI5CY
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2015-09-09 18:35:07 +02:00 |
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include
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Rename instr_core_intf to prefetch_buffer, add if_busy signal again
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2015-09-10 13:12:19 +02:00 |
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.gitignore
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Added vim swap file
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2015-07-24 15:26:32 +02:00 |
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alu.sv
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Use 'x to simplify synthesis
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2015-09-02 09:25:06 +02:00 |
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compressed_decoder.sv
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Prefetcher basically done, works in pulpino without rvc
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2015-09-10 13:12:19 +02:00 |
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controller.sv
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Fix misaligned access, they did not correctly forward and used the wrong
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2015-09-14 12:46:46 +02:00 |
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cs_registers.sv
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Add performance counter for compressed instructions
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2015-09-08 17:24:39 +02:00 |
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debug_unit.sv
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Rework pipeline flushes and exceptions
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2015-08-31 10:02:55 +02:00 |
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ex_stage.sv
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More cleanup, remove unused signal
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2015-09-05 16:33:51 +02:00 |
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exc_controller.sv
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Simplify exception controller and make sure external IRQs work as well
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2015-09-11 14:06:38 +02:00 |
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hwloop_controller.sv
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Finish hwloops addition
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2015-09-07 03:40:28 +02:00 |
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hwloop_regs.sv
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Cleanup unneeded signals and dead code
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2015-09-02 18:07:44 +02:00 |
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id_stage.sv
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Fix misaligned access, they did not correctly forward and used the wrong
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2015-09-14 12:46:46 +02:00 |
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if_stage.sv
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Oops... is_compressed can of course no longer be generated in id stage
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2015-09-11 17:42:15 +02:00 |
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load_store_unit.sv
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Change LSU to use correct protocol
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2015-09-10 13:12:19 +02:00 |
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mult.sv
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Fix linting errors/warnings and remove dead signals
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2015-08-28 17:15:55 +02:00 |
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prefetch_buffer.sv
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Rename instr_core_intf to prefetch_buffer, add if_busy signal again
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2015-09-10 13:12:19 +02:00 |
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register_file.sv
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Fix linting errors/warnings and remove dead signals
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2015-08-28 17:15:55 +02:00 |
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riscv_core.sv
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Oops... is_compressed can of course no longer be generated in id stage
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2015-09-11 17:42:15 +02:00 |
