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update riscv_core_setting (#633)

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Signed-off-by: Udi <udij@google.com>
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udinator 2020-02-28 17:02:07 -08:00 • committed by GitHub
parent 59b3f7f476
commit d8b9737039
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1 changed files with 4 additions and 1 deletions
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dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv
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@ -26,6 +26,9 @@ parameter int VLEN = 512;
parameter int ELEN = 64;
parameter int SLEN = 64;
// Number of harts
parameter int NUM_HARTS = 1;
// Parameter for SATP mode, set to BARE if address translation is not supported
parameter satp_mode_t SATP_MODE = BARE;
@ -67,7 +70,7 @@ bit support_sfence = 0;
//-----------------------------------------------------------------------------
// Number of kernel data pages
int num_of_kernel_data_pages = 2;
int num_of_kernel_data_pages = 0;
// Byte size of kernel data pages
int kernel_data_page_size = 4096;