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Add chapters about hardware loops and multiply-accumulate
Add instruction specification of pulp extensions
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Andreas Traber
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4 changed files with 283 additions and 7 deletions
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\chapter{PULP Hardware Loop Extensions}
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\label{chap:hwloop}
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For increased efficiency of small loops, RI5CY supports hardware loops.
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Hardware loops make it possible to execute a piece of code multiple times,
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without the overhead of branches or updating a counter. Hardware loops involve
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zero stall cycles for jumping to the first instruction of a loop.
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A hardware loop is defined by its start address (pointing to the first
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instruction in the loop), its end address (pointing to the instruction that
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will be executed last in the loop) and a counter that is decremented every time
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the loop body is executed. RI5CY contains two hardware loop register sets, each
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of them can store these three values.
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If the end address of the two hardware loops is identical, loop 0 has higher
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priority and only the loop counter for hardware loop 0 is decremented.
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The instructions described below are used to setup the hardware loop registers.
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Note that the minimum loop size is two instructions.
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For debugging and context switches the hardware loop registers are mapped into
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the CSR address space and thus it is possible to read and write them via
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\instr{csrr} and \instr{csrw} instructions.
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\section{Instructions}
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\subsection{lp.starti L, uimmL}
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Sets the start address of a hardware loop.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ uimmL[11:0] }
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\bitbox[]{5}{ 00000 }
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\bitbox[]{3}{ 000 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpstart[L] = pc + (Zext(uimmL[11:0]) << 1)}
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\subsection{lp.endi L, uimmL}
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Sets the end address of a hardware loop.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ uimmL[11:0] }
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\bitbox[]{5}{ 00000 }
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\bitbox[]{3}{ 001 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpend[L] = pc + (Zext(uimmL[11:0]) << 1)}
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\subsection{lp.count L, rs1}
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Sets the number of iterations of a hardware loop.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ 0000 0000 0000}
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\bitbox[]{5}{ src1 }
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\bitbox[]{3}{ 010 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpcount[L] = rs1}
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\subsection{lp.counti L, uimmL}
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Sets the number of iterations of a hardware loop.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ uimmL[11:0] }
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\bitbox[]{5}{ 00000 }
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\bitbox[]{3}{ 011 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpcount[L] = Zext(uimmL[11:0])}
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\subsection{lp.setup L, rs1, uimmL}
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Sets up a hardware loop in one instruction. This instruction assumes that the
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next instruction is the start address of the loop.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ uimmL[11:0] }
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\bitbox[]{5}{ src1 }
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\bitbox[]{3}{ 100 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpstart[L] = pc + 4; lpend[L] = pc + Zext(uimmL[11:0]); lpcount[L] = rs1}
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\subsection{lp.setupi L, uimmS, uimmL}
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Sets up a hardware loop in one instruction. This instruction assumes that the
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next instruction is the start address of the loop. The number of iterations is
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given as an immediate.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,20,19,15,14,12,11,7,6,0} \\
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\bitbox{12}{ uimmL[11:0] }
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\bitbox{5}{ uimmS }
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\bitbox{3}{ funct3 }
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\bitbox{4}{ 0000 }
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\bitbox{1}{ L }
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\bitbox{7}{ opcode } \\
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\bitbox[]{12}{ uimmL[11:0] }
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\bitbox[]{5}{ uimmS }
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\bitbox[]{3}{ 101 }
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\bitbox[]{4}{ 0000 }
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\bitbox[]{1}{ L }
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\bitbox[]{7}{ 111 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{lpstart[L] = pc + 4; lpend[L] = pc + Zext(uimmL[11:0]); lpcount[L] = Zext(uimmS)}
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\section{CSR Mapping}
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\begin{table}[H]
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\caption{Control and Status Register Map}
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\label{tab:csr_map}
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\centering\begin{tabularx}{\linewidth}{@{}|cc|c|l|l|X|@{}} \toprule
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\multicolumn{2}{|c|}{\textbf{CSR Address}} & \textbf{Hex} & \textbf{Name} & \textbf{Access} & \textbf{Description} \\ \hline
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\textbf{[11:6]} & \textbf{[5:0]} & & & & \\ \toprule
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011110 & 110000 & 0x7B0 & lpstart[0] & R/W & Hardware Loop 0 Start \\ \hline
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011110 & 110001 & 0x7B1 & lpend[0] & R/W & Hardware Loop 0 End \\ \hline
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011110 & 110010 & 0x7B2 & lpcount[0] & R/W & Hardware Loop 0 Counter \\ \hline
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011110 & 110100 & 0x7B4 & lpstart[1] & R/W & Hardware Loop 1 Start \\ \hline
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011110 & 110101 & 0x7B5 & lpend[1] & R/W & Hardware Loop 1 End \\ \hline
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011110 & 110110 & 0x7B6 & lpcount[1] & R/W & Hardware Loop 1 Counter \\ \bottomrule
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\end{tabularx}
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\end{table}
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@ -1,7 +1,89 @@
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\chapter{Multiply-Accumulate}
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\label{chap:mac}
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\rvcore uses a single-cycle 32 bit lower result multiplier. Only a subset of the
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standard M extension is implemented, i.e. the \instr{mul} instruction.
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Divisions and multiplications that return the upper half of the result are not
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supported.
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\rvcore uses a single-cycle 32-bit $\times$ 32-bit multiplier with a 32-bit
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result. Only a subset of the standard M extension is implemented, i.e. the
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\instr{mul} instruction. Divisions and multiplications that return the upper
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32-bit of the result are not supported.
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Specifically the following instruction is supported:
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\begin{itemize}
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\item \instr{mul}
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\end{itemize}
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The following instructions are \textbf{not} supported:
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\begin{itemize}
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\item \instr{mulh}
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\item \instr{mulhs}
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\item \instr{mulhu}
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\item \instr{div}
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\item \instr{divu}
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\item \instr{rem}
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\item \instr{remu}
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\end{itemize}
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Instead \rvcore supports non-standard extensions for multiply-accumulate and
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half-word multiplications.
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\section{Instructions}
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\subsection{p.mac rD, rs1, rs2}
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Multiply-Accumulate on 32-bit $\times$ 32-bit with a 32-bit result.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,30,29,25,24,20,19,15,14,12,11,7,6,0} \\
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\bitbox{2}{ 00 }
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\bitbox{5}{ rs3 }
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\bitbox{5}{ rs2 }
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\bitbox{5}{ rs1 }
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\bitbox{3}{ funct3 }
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\bitbox{5}{ rd }
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\bitbox{7}{ opcode } \\
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\bitbox[]{2}{ 00 }
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\bitbox[]{5}{ src3 }
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\bitbox[]{5}{ src2 }
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\bitbox[]{5}{ src1 }
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\bitbox[]{3}{ 000 }
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\bitbox[]{5}{ dest }
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\bitbox[]{7}{ 101 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{rD = rs1 * rs2 + rs3}
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\subsection{p.mac\{.zl,.sl,.zh,.sh\}\{.zl,.sl,.zh,.sh\} rD, rs1, rs2}
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Multiply-Accumulate on 16-bit $\times$ 16-bit with a 32-bit result. The
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half-word and sign-mode that is used for the multiplication can be selected.
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\begin{center}
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\begin{bytefield}[endianness=big,bitwidth=1.3em]{32}
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\bitheader{31,30,29,25,24,20,19,15,14,12,11,7,6,0} \\
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\bitbox{1}{ S1 }
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\bitbox{1}{ S2 }
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\bitbox{5}{ rs3 }
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\bitbox{5}{ rs2 }
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\bitbox{5}{ rs1 }
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\bitbox{1}{ 1 }
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\bitbox{1}{ H1 }
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\bitbox{1}{ H2 }
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\bitbox{5}{ rd }
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\bitbox{7}{ opcode } \\
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\bitbox[]{1}{ S1 }
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\bitbox[]{1}{ S2 }
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\bitbox[]{5}{ unused }
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\bitbox[]{5}{ src2 }
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\bitbox[]{5}{ src1 }
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\bitbox[]{1}{ 0 }
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\bitbox[]{1}{ H1 }
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\bitbox[]{1}{ H2 }
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\bitbox[]{5}{ dest }
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\bitbox[]{7}{ 101 1011 }
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\end{bytefield}
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\end{center}
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\textbf{Operation:} \texttt{rD = rs1[H1*16+15:H1*16] * rs2[H2*16+15:H2*16] + rs3}
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S1 and S2 determine the zero/sign-extension of rs1 and rs2. A value of
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\texttt{1} means sign-extension.
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@ -27,10 +27,10 @@ Figure~\ref{fig:ri5cy_overview} shows a block diagram of the core.
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Only the \instr{mul} instruction is supported.
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\item PULP specific extensions \\
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\begin{itemize}
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\item Hardware Loops, see Chapter~\ref{chap:hwloop}
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\item ALU extensions, see Chapter~\ref{chap:aluext}
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\item Multiply-Accumulate extensions, see Chapter~\ref{chap:mac}
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\item Post-Incrementing load and stores, see Chapter~\ref{chap:lsu}
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\item Multiply-Accumulate extensions, see Chapter~\ref{chap:mac}
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\item ALU extensions, see Chapter~\ref{chap:aluext}
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\item Hardware Loops, see Chapter~\ref{chap:hwloop}
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\end{itemize}
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\end{itemize}
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@ -107,3 +107,11 @@
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\caption{#3}
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\end{figure}}
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\newcommand\instrDesc[3]{%
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\subsection{#1}
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\begin{center}
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#3
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\end{center}
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\textbf{Operation:} \texttt{#2}%
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}
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