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Added more information about debug to documentation
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Andreas Traber
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3 changed files with 154 additions and 30 deletions
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\chapter{Debug}
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\label{chap:debug}
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\rvcore has full support for software breakpoints (\instr{ebreak}), access to
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general-purpose and control and status registers via a debug port. It is also
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possible to halt the core from the debug port and put it into single-stepping
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mode. Similarly when an interrupt occurs, instead of jumping to the interrupt
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handler the core can trap to an attached debugger.
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The debug port uses the following interface:
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\begin{table}[H]
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\caption{Debug Signals}
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\label{tab:debug_signals}
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\begin{tabularx}{\textwidth}{@{}llX@{}} \toprule
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\textbf{Signal} & \textbf{Direction} & \textbf{Description} \\ \toprule
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\signal{dbginf\_strobe\_i} & \textbf{input} & Command request \\ \hline
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\signal{dbginf\_we\_i} & \textbf{input} & Write Enable \\ \hline
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\signal{dbginf\_addr\_i[15:0]} & \textbf{input} & Address \\ \hline
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\signal{dbginf\_data\_i[31:0]} & \textbf{input} & Input data \\ \hline
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\signal{dbginf\_data\_o} & \textbf{output} & Output data \\ \hline
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\signal{dbginf\_ack\_o} & \textbf{output} & Command was executed \\ \hline
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\signal{dbginf\_stall\_i} & \textbf{input} & Stall the core \\ \hline
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\signal{dbginf\_bp\_o} & \textbf{output} & Breakpoint hit \\ \bottomrule
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\end{tabularx}
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\end{table}
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This interface is natively supported by the advanced debug bridge that is used
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by \pulp and \pulpino, see also the documentation of this bridge.
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\section{Debug Address Map}
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This debug address map is not optimal and should be changed!
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See the OpenSoC debug project for a proposal for a better address map.
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\begin{table}[H]
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\caption{Control and Status Register Map}
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\label{tab:debug_map}
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\centering\begin{tabularx}{\linewidth}{@{}|cc|c|l|X|@{}} \toprule
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\multicolumn{2}{|c|}{\textbf{Dbginf Addr [15:0]}} & \textbf{Hex} & \textbf{Name} & \textbf{Description} \\ \hline
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Grp [15:11] & Addr [10:0] & & & \\ \toprule
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\texttt{0\_0001} & \texttt{000\_000X\_XXXX} & \texttt{0x0800 - 0x081F} & GPR & General-Purpose Registers \\ \hline
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\texttt{0\_0110} & \texttt{000\_0000\_0000} & \texttt{0x3000 - 0x3014} & Debug & Debug Registers \\ \hline
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\texttt{?\_????} & \texttt{XXX\_XXXX\_XXXX} & \texttt{ } & CSR & Everything else is mapped to CSR \\ \bottomrule
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\end{tabularx}
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\end{table}
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\subsection{Debug Register: DMR1}
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\textbf{CSR Address:} \texttt{0x3010} \\
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\textbf{Reset Value:} \texttt{0x0000\_0000} \\
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\begin{figure}[H]
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\centering
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,23,22,0} \\
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\bitbox{9}{ Unused }
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\bitbox{1}{\rotatebox{90}{\tiny Single-Stepping }}
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\bitbox{22}{ Unused }
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\end{bytefield}
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\caption{DMR1}
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\end{figure}
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Single-stepping activates single-stepping mode, meaning the core traps to the
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debugger after one instruction has been executed.
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\subsection{Debug Register: DSR}
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\textbf{CSR Address:} \texttt{0x3014} \\
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\textbf{Reset Value:} \texttt{0x0000\_0000} \\
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\begin{figure}[H]
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\centering
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,8,7,6,0} \\
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\bitbox{24}{ Unused }
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\bitbox{1}{\rotatebox{90}{\tiny INTE }}
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\bitbox{1}{\rotatebox{90}{\tiny IIE }}
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\bitbox{6}{ Unused }
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\end{bytefield}
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\caption{DMR1}
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\end{figure}
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\signal{IIE} stands for illegal instruction exception enabled. A value of
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\signal{1} means trap to the debugger when an illegal instruction is
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encountered.
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\signal{INTE} stands for interrupt enabled. A value of \signal{1} means trap to
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the debugger when an interrupt is encountered.
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@ -1,4 +1,53 @@
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\chapter{Exceptions and Interrupts}
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\label{chap:exceptions}
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\rvcore supports
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\rvcore supports vectorized interrupts, exceptions on illegal instructions and
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exceptions on load and store instructions to invalid addresses.
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\begin{table}[H]
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\caption{Interrupt/exception offset vector table}
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\label{tab:exc_table}
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\centering\begin{tabular}{@{}ll@{}} \toprule
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\textbf{Address} & \textbf{Description} \\ \toprule
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\signal{0x00} - \signal{0x0000\_007C} & Interrupts 0 - 31 \\ \hline
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\signal{0x80} & Reset \\ \hline
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\signal{0x84} & Illegal Instruction \\ \hline
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\signal{0x88} & \instr{ECALL} instruction executed \\ \hline
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\signal{0x8C} & LSU error (invalid memory access) \\ \bottomrule
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\end{tabular}
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\end{table}
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The instruction addresses in Table~\ref{tab:exc_table} are considered as an
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offset to the boot address given to the core. Specifically the core jumps to
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address \signal{$\{$boot\_addr[31:8], offset[7:0]$\}$} when encountering an
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exception/interrupt.
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\section{Interrupts}
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\rvcore uses vectorized interrupts, specifically it provides 32 separate
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interrupt lines. Interrupts can only be enabled/disabled on a global basis and
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not individually. It is assumed that there is an event/interrupt controller
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outside of the core that performs masking and buffering of the interrupt lines.
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The global interrupt enable is done via the CSR register \signal{mstatus}.
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\section{Exceptions}
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The illegal instruction exception, the load and store invalid memory access
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exceptions and ecall instruction exceptions can not be disabled and are always
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active.
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The illegal instruction exception and the load and store invalid memory access
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exceptions are precise exceptions, i.e. the value of \signal{mepc} will be the
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instruction address that caused it.
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\section{Handling}
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\rvcore does not support nested interrupt/exception handling. Exceptions inside
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interrupt/exception handlers are ignored and thus a user must ensure that such
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a situation does not happen, as otherwise the behaviour is undefined.
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Upon executing an \instr{eret} instruction, the core jumps to the program
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counter saved in the CSR register \signal{mepc}. When entering an
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interrupt/exception handler, the core sets \signal{mepc} to the current program
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counter.
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@ -1,27 +1,15 @@
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\chapter{Performance Counters}
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\label{chap:perf_count}
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Performance Counters in \orion are placed inside the Special-Purpose Registers
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and can be accessed with \instr{l.mfspr} and \instr{l.mtspr}.
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Figure~\ref{fig:spr_addr} shows the SPR address format and
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Table~\ref{tab:pc_spr_addr} shows the respective addresses for configuration and
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access to the performance counters.
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\begin{table}[H]
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\caption{PC SPR Addresses}
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\label{tab:pc_spr_addr}
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\centering\begin{tabularx}{\textwidth}{@{}ccccX@{}} \toprule
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\textbf{Group \#} & \textbf{Reg \#} & Reg Name & Access & Description\\ \toprule
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7 & 0 - 31 & PCCR0-PCCR31 & R/W & Performance Counters Count Registers \\ \hline
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7 & 32 & PCER & R/W & Performance Counters Event Register \\ \hline
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7 & 33 & PCMR & R/W & Performance Counters Mode Register \\ \bottomrule
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\end{tabularx}
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\end{table}
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Performance Counters in \rvcore are placed inside the Control and Status
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Registers and can be accessed with \instr{csrr} and \instr{csrw} instructions.
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See Table~\ref{tab:csr_map} for the address map of the performance counter
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registers.
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\section{Performance Counter Mode Register (PCMR)}
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\csrDesc{0x3821}{0x0000\_0003}{PCMR}{
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\csrDesc{0x7A1}{0x0000\_0003}{PCMR}{
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,1,0} \\
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\bitbox{30}{ Unused }
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@ -30,17 +18,17 @@ access to the performance counters.
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\end{bytefield}
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}
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The \instr{Global Enable} bit controls all performance counters, i.e. if it is set
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to \instr{0}, all performance counters are deactivated.
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After reset, the \instr{Global Enable} bit is set.
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The \instr{Global Enable} bit controls all performance counters, i.e. if it is
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set to \instr{0}, all performance counters are deactivated. After reset, the
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\instr{Global Enable} bit is set.
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The \instr{Saturation} bit controls saturation behaviour of the performance
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counters. If it is set, saturating arithmetic is used.
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After reset, the \instr{Saturation} bit is set.
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counters. If it is set, saturating arithmetic is used. After reset, the
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\instr{Saturation} bit is set.
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\section{Performance Counter Event Register (PCER)}
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\csrDesc{0x3820}{0x0000\_0000}{PCER}{
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\csrDesc{0x7A0}{0x0000\_0000}{PCER}{
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} \\
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\bitbox{1}{\rotatebox{90}{\tiny (ALL) }}
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@ -80,7 +68,7 @@ accesses separately.
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\section{Performance Counter Counter Registers (PCCR0-31)}
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\csrDesc{0x3800 - 0x381F}{0x0000\_0000}{PCCR0-31}{
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\csrDesc{0x780 - 0x79F}{0x0000\_0000}{PCCR0-31}{
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\begin{bytefield}[endianness=big]{32}
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\bitheader{31,0} \\
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\bitbox{32}{Unsigned integer counter value}
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@ -104,11 +92,11 @@ controlled by the \instr{saturation} bit in PCMR.
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\textbf{PCCR8} & \textbf{BRANCH} & Number of branches, counts taken and not taken branches\\ \hline
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\textbf{PCCR9} & \textbf{BTAKEN} & Number of taken branches \\ \hline
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\textbf{PCCR10} & \textbf{RVC} & Number of compressed instructions executed \\ \hline
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\textbf{PCCR11} & \textbf{LD\_EXT} & Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline
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\textbf{PCCR12} & \textbf{ST\_EXT} & Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline
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\textbf{PCCR13} & \textbf{LD\_EXT\_CYC} & Cycles used for memory loads to EXT. Every non-TCDM access is considered external \\ \hline
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\textbf{PCCR14} & \textbf{ST\_EXT\_CYC} & Cycles used for memory stores to EXT. Every non-TCDM access is considered external \\ \hline
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\textbf{PCCR15} & \textbf{TCDM\_CONT} & Cycles wasted due to TCDM/log-interconnect contention \\ \hline
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\textbf{PCCR11} & \textbf{LD\_EXT} & Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external (PULP only) \\ \hline
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\textbf{PCCR12} & \textbf{ST\_EXT} & Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external (PULP only) \\ \hline
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\textbf{PCCR13} & \textbf{LD\_EXT\_CYC} & Cycles used for memory loads to EXT. Every non-TCDM access is considered external (PULPY only) \\ \hline
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\textbf{PCCR14} & \textbf{ST\_EXT\_CYC} & Cycles used for memory stores to EXT. Every non-TCDM access is considered external (PULPY only) \\ \hline
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\textbf{PCCR15} & \textbf{TCDM\_CONT} & Cycles wasted due to TCDM/log-interconnect contention (PULPY only) \\ \hline
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\textbf{PCCR31} & \textbf{ALL} & Special Register, a write to this register will set all counters to the supplied value\\ \bottomrule
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\end{tabularx}
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\end{table}
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