new interrupt protocol

zeroriscy_controller.sv

@@ -85,6 +85,7 @@ module zeroriscy_controller
   input  logic        m_IE_i,                     // interrupt enable bit from CSR (M mode)
 
   output logic        irq_ack_o,
+  output logic [4:0]  irq_id_o,
 
   output logic [5:0]  exc_cause_o,
   output logic        exc_ack_o,
@@ -190,7 +191,7 @@ module zeroriscy_controller
     halt_id_o              = 1'b0;
     dbg_ack_o              = 1'b0;
     irq_ack_o              = 1'b0;
-
+    irq_id_o               = irq_id_ctrl_i;
     irq_enable_int         = m_IE_i;
 
     // a trap towards the debug unit is generated when one of the

zeroriscy_core.sv

@@ -73,6 +73,7 @@ module zeroriscy_core
   input  logic        irq_i,                 // level sensitive IR lines
   input  logic [4:0]  irq_id_i,
   output logic        irq_ack_o,             // irq ack
+  output logic [4:0]  irq_id_o,
 
   // Debug Interface
   input  logic        debug_req_i,
@@ -425,6 +426,7 @@ module zeroriscy_core
     .irq_id_i                     ( irq_id_i             ),
     .m_irq_enable_i               ( m_irq_enable         ),
     .irq_ack_o                    ( irq_ack_o            ),
+    .irq_id_o                     ( irq_id_o             ),
 
     .lsu_load_err_i               ( lsu_load_err         ),
     .lsu_store_err_i              ( lsu_store_err        ),

zeroriscy_id_stage.sv

@@ -120,6 +120,7 @@ module zeroriscy_id_stage
     input  logic [4:0]  irq_id_i,
     input  logic        m_irq_enable_i,
     output logic        irq_ack_o,
+    output logic [4:0]  irq_id_o,
     output logic [5:0]  exc_cause_o,
 
     input  logic        lsu_load_err_i,
@@ -561,6 +562,7 @@ module zeroriscy_id_stage
     .m_IE_i                         ( m_irq_enable_i         ),
 
     .irq_ack_o                      ( irq_ack_o              ),
+    .irq_id_o                       ( irq_id_o               ),
 
     .exc_ack_o                      ( exc_ack                ),
     .exc_kill_o                     ( exc_kill               ),