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Remove dead signals
This commit is contained in:
Andreas Traber
parent
aaf3aca410
commit
e9d3ab56b7
5 changed files with 3 additions and 40 deletions
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@ -68,8 +68,6 @@ module controller
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output logic mult_use_carry_o, // Use carry for MAC
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output logic mult_mac_en_o, // Use the accumulator after multiplication
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output logic regfile_wdata_mux_sel_o, // Mul selctor used in WB stage to select regfile wdata from ex result (ALU-MUL), from data memory, or special registers
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input logic regfile_wdata_mux_sel_ex_i, // FW signal: Mul selctor used in WB stage to select regfile wdata from ex result (ALU-MUL), from data memory, or special registers
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output logic regfile_we_o, // Write Enable to regfile
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output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations
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@ -208,7 +206,6 @@ module controller
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mult_use_carry_o = 1'b0;
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mult_mac_en_o = 1'b0;
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regfile_wdata_mux_sel_o = 1'b1; // TODO: Remove, no longer used
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regfile_we = 1'b0;
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regfile_alu_we = 1'b0;
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regfile_alu_waddr_mux_sel_o = 2'b01;
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@ -69,7 +69,6 @@ module ex_stage
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// directly passed through to WB stage, not used in EX
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input logic regfile_we_i,
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input logic [4:0] regfile_waddr_i,
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input logic regfile_wdata_mux_sel_i,
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input logic [31:0] regfile_rb_data_i,
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@ -83,7 +82,6 @@ module ex_stage
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// Output of EX stage pipeline
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output logic [4:0] regfile_waddr_wb_o,
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output logic regfile_wdata_mux_sel_wb_o,
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output logic regfile_we_wb_o,
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output logic [31:0] regfile_rb_data_wb_o,
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@ -220,7 +218,6 @@ module ex_stage
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if (rst_n == 1'b0)
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begin
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regfile_waddr_wb_o <= 5'b0_0000;
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regfile_wdata_mux_sel_wb_o <= 1'b0;
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regfile_we_wb_o <= 1'b0;
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regfile_rb_data_wb_o <= 32'h0000_0000;
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end
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@ -230,7 +227,6 @@ module ex_stage
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begin
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regfile_we_wb_o <= regfile_we_i;
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regfile_waddr_wb_o <= regfile_waddr_i;
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regfile_wdata_mux_sel_wb_o <= regfile_wdata_mux_sel_i;
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regfile_rb_data_wb_o <= regfile_rb_data_i;
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end
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end
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@ -85,7 +85,6 @@ module id_stage
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output logic mult_mac_en_ex_o,
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output logic [4:0] regfile_waddr_ex_o,
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output logic regfile_wdata_mux_sel_ex_o,
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output logic regfile_we_ex_o,
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output logic [4:0] regfile_alu_waddr_ex_o,
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@ -232,7 +231,6 @@ module id_stage
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logic mult_mac_en; // Enables the use of the accumulator
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// Register Write Control
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logic regfile_wdata_mux_sel;
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logic regfile_we_id;
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logic [1:0] regfile_alu_waddr_mux_sel; // TODO: FixMe -> 1bit
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@ -567,8 +565,6 @@ module id_stage
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.mult_mac_en_o ( mult_mac_en ),
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// Register file control signals
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.regfile_wdata_mux_sel_o ( regfile_wdata_mux_sel ),
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.regfile_wdata_mux_sel_ex_i ( regfile_wdata_mux_sel_ex_o ),
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.regfile_we_o ( regfile_we_id ),
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.regfile_alu_we_o ( regfile_alu_we_id ),
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@ -765,7 +761,6 @@ module id_stage
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mult_mac_en_ex_o <= 1'b0;
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regfile_waddr_ex_o <= 5'b0;
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regfile_wdata_mux_sel_ex_o <= 1'b0;
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regfile_we_ex_o <= 1'b0;
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regfile_alu_waddr_ex_o <= 5'b0;
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@ -833,7 +828,6 @@ module id_stage
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regfile_waddr_ex_o <= regfile_waddr_id;
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regfile_wdata_mux_sel_ex_o <= regfile_wdata_mux_sel;
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regfile_we_ex_o <= regfile_we_id;
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regfile_alu_waddr_ex_o <= regfile_alu_waddr_id;
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@ -130,12 +130,10 @@ module riscv_core
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// Register Write Control
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logic [4:0] regfile_waddr_ex;
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logic regfile_wdata_mux_sel_ex;
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logic regfile_we_ex;
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logic [4:0] regfile_waddr_fw_wb_o; // From WB to ID
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logic regfile_we_wb;
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logic [31:0] regfile_wdata;
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logic regfile_wdata_mux_sel_wb;
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logic [4:0] regfile_alu_waddr_ex;
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logic regfile_alu_we_ex;
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@ -163,7 +161,6 @@ module riscv_core
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logic [31:0] data_addr_ex;
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logic data_misaligned_ex;
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logic [31:0] data_rdata_int;
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logic [31:0] lsu_data_reg;
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logic data_ack_int;
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// Signals between instruction core interface and pipe (if and id stages)
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@ -379,7 +376,6 @@ module riscv_core
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.mult_mac_en_ex_o ( mult_mac_en_ex ), // from ID to EX stage
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.regfile_waddr_ex_o ( regfile_waddr_ex ),
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.regfile_wdata_mux_sel_ex_o ( regfile_wdata_mux_sel_ex ),
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.regfile_we_ex_o ( regfile_we_ex ),
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.regfile_alu_we_ex_o ( regfile_alu_we_ex ),
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@ -494,7 +490,6 @@ module riscv_core
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// From ID Stage: Regfile control signals
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.regfile_waddr_i ( regfile_waddr_ex ),
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.regfile_wdata_mux_sel_i ( regfile_wdata_mux_sel_ex ),
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.regfile_we_i ( regfile_we_ex ),
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.regfile_alu_we_i ( regfile_alu_we_ex ),
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@ -510,7 +505,6 @@ module riscv_core
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// Output of ex stage pipeline
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.regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ),
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.regfile_wdata_mux_sel_wb_o ( regfile_wdata_mux_sel_wb ),
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.regfile_we_wb_o ( regfile_we_wb ),
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.regfile_rb_data_wb_o ( regfile_rb_data_wb ),
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@ -545,13 +539,11 @@ module riscv_core
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// \_/\_/ |____/ |____/ |_/_/ \_\____|_____| //
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// //
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/////////////////////////////////////////////////////////
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// TODO: the wb stage does absolutely nothing anymore, consider removing it
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wb_stage wb_stage_i
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(
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// Mux selector of regfile wdata
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.regfile_wdata_mux_sel_i ( regfile_wdata_mux_sel_wb ),
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// Mux inputs
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.data_rdata_i ( data_rdata_int ),
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.lsu_data_reg_i ( lsu_data_reg ),
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// Mux output
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.regfile_wdata_o ( regfile_wdata )
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);
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@ -578,7 +570,6 @@ module riscv_core
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.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
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.data_rdata_ex_o ( data_rdata_int ),
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.lsu_data_reg_o ( lsu_data_reg ),
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.data_req_ex_i ( data_req_ex ),
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.data_addr_ex_i ( data_addr_ex ),
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.data_ack_int_o ( data_ack_int ), // ack used in controller to stall
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19
wb_stage.sv
19
wb_stage.sv
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@ -37,29 +37,14 @@
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module wb_stage
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(
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// MUX SELECTOR --> Used to select what write in the register file
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input logic regfile_wdata_mux_sel_i, // Comes from the controller (thru id-ex and ex-wb pipe)
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// MUX INPUTS
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input logic [31:0] data_rdata_i, // read Data from data memory system
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input logic [31:0] lsu_data_reg_i, // TODO: remove; read data registered in LSU
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// MUX OUTPUT
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output logic [31:0] regfile_wdata_o // write data for register file
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);
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// TODO: Remove this mux and the associated signals
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// Register Write Data Selection --> Data to write in the regfile
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// Select between:
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// 0: From Special Register
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// 1: From Data Memory
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always_comb
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begin : REGFILE_WDATA_MUX
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case (regfile_wdata_mux_sel_i)
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//1'b0: regfile_wdata_o = sp_rdata_i;
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1'b1: regfile_wdata_o = data_rdata_i;
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default: regfile_wdata_o = data_rdata_i;
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endcase; // case (regfile_wdata_mux_sel_i)
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end
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assign regfile_wdata_o = data_rdata_i;
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endmodule
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