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[DV] Fix implemented_csr[] compile issue (#346)

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udinator 2019-09-23 17:49:40 -07:00 • committed by GitHub
parent 9b967a5d97
commit ec02461b4a
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1 changed files with 2 additions and 2 deletions
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dv/uvm/riscv_dv_extension/riscv_core_setting.sv
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@ -29,7 +29,7 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
// Unsupported instructions
// Avoid generating these instructions in regular regression
// FENCE.I is intentionally treated as illegal instruction by ibex core
riscv_instr_name_t unsupported_instr[] = {FENCEI};
riscv_instr_name_t unsupported_instr[] = {FENCE_I};
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
@ -71,7 +71,7 @@ int kernel_program_instr_cnt = 400;
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
privileged_reg_t implemented_csr[$] = {
parameter privileged_reg_t implemented_csr[] = {
// Machine mode mode CSR
MVENDORID, // Vendor ID
MARCHID, // Architecture ID