github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 12:57:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update docs for (s/ms)context

Browse source
This commit is contained in:
Harry Callahan 2022-10-05 11:31:07 +01:00
parent 836bd67531
commit ee7854fd3a
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
doc/03_reference/cs_registers.rst
View file

@ -46,6 +46,8 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
+---------+--------------------+--------+-----------------------------------------------+
| 0x3BF | ``pmpaddr15`` | WARL | PMP Address Register |
+---------+--------------------+--------+-----------------------------------------------+
| 0x5A8 | ``scontext`` | WARL | Supervisor Context Register |
+---------+--------------------+--------+-----------------------------------------------+
| 0x747 | ``mseccfg`` | WARL | Machine Security Configuration |
+---------+--------------------+--------+-----------------------------------------------+
| 0x757 | ``mseccfgh`` | WARL | Upper 32 bits of ``mseccfg`` |
@ -60,7 +62,7 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
+---------+--------------------+--------+-----------------------------------------------+
| 0x7A8 | ``mcontext`` | WARL | Machine Context Register |
+---------+--------------------+--------+-----------------------------------------------+
| 0x7AA | ``scontext`` | WARL | Supervisor Context Register |
| 0x7AA | ``mscontext`` | WARL | Machine Supervisor Context Register |
+---------+--------------------+--------+-----------------------------------------------+
| 0x7B0 | ``dcsr`` | WARL | Debug Control and Status Register |
+---------+--------------------+--------+-----------------------------------------------+