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disabled lsu error and fixed misaligned

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This commit is contained in:
Pasquale Davide Schiavone 2017-01-26 17:18:53 +01:00
parent 3d2a02083f
commit f80a14b7c2
4 changed files with 15 additions and 16 deletions
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4
controller.sv
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@ -62,7 +62,7 @@ module littleriscv_controller
// LSU
input logic data_req_ex_i, // data memory access is currently performed in EX stage
input logic data_misaligned_fsm_i,
input logic data_misaligned_i,
input logic data_load_event_i,
// jump/branch signals
@ -525,7 +525,7 @@ module littleriscv_controller
// Forwarding EX -> ID
// for misaligned memory accesses
if (data_misaligned_fsm_i)
if (data_misaligned_i)
begin
operand_a_fw_mux_sel_o = SEL_MISALIGNED;
operand_b_fw_mux_sel_o = SEL_REGFILE;

9
exc_controller.sv
View file

@ -88,11 +88,10 @@ module littleriscv_exc_controller
// request for exception/interrupt
assign int_req_int = ecall_insn_i
| illegal_insn_i;
assign ext_req_int = lsu_load_err_i
| lsu_store_err_i
| irq_enable_i & irq_i;
| illegal_insn_i
| lsu_load_err_i
| lsu_store_err_i;
assign ext_req_int = irq_enable_i & irq_i;
assign req_int = int_req_int | ext_req_int;

14
id_stage.sv
View file

@ -254,7 +254,6 @@ module littleriscv_id_stage
logic [1:0] data_reg_offset_id;
logic data_req_id;
logic data_load_event_id;
logic data_misaligned_fsm;
// CSR control
logic csr_access;
@ -364,18 +363,17 @@ module littleriscv_id_stage
endcase
end
// Operand a forwarding mux
always_comb
begin : operand_a_fw_mux
case (operand_a_fw_mux_sel)
SEL_MISALIGNED: operand_a_fw_id = misaligned_addr_i;
SEL_FW_WB: operand_a_fw_id = regfile_wdata_wb_i;
SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id;
default: operand_a_fw_id = regfile_data_ra_id;
SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id;
default: operand_a_fw_id = regfile_data_ra_id;
endcase; // case (operand_a_fw_mux_sel)
end
//////////////////////////////////////////////////////
// ___ _ ____ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | | __ ) //
@ -428,7 +426,7 @@ module littleriscv_id_stage
assign alu_operand_b = operand_b;
/*
// Operand b forwarding mux
always_comb
begin : operand_b_fw_mux
@ -438,7 +436,9 @@ module littleriscv_id_stage
default: operand_b_fw_id = regfile_data_rb_id;
endcase; // case (operand_b_fw_mux_sel)
end
*/
assign operand_b_fw_id = regfile_data_rb_id;
//////////////////////////////////////////////////////
// ___ _ ____ //
@ -598,7 +598,7 @@ module littleriscv_id_stage
// LSU
.data_req_ex_i ( data_req_ex_o ),
.data_misaligned_fsm_i ( data_misaligned_fsm ),
.data_misaligned_i ( data_misaligned_i ),
.data_load_event_i ( data_load_event_ex_o ),
// jump/branch control

4
load_store_unit.sv
View file

@ -344,8 +344,8 @@ module littleriscv_load_store_unit
assign load_err_o = data_gnt_i && data_err_i && ~data_we_o;
assign store_err_o = data_gnt_i && data_err_i && data_we_o;
assign load_err_o = 1'b0;
assign store_err_o = 1'b0;
// FSM
always_comb