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Cleanup includes and defines

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- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
  directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
  SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
  be set through command-line flags to the simulation/synthesis tools.

Initial version by Nils Gräf.
This commit is contained in:
Philipp Wagner 2019-05-03 11:00:46 +01:00 • committed by Philipp Wagner
parent 42ba856ecc
commit f9ad280d0c
20 changed files with 9 additions and 77 deletions
Download patch file Download diff file Expand all files Collapse all files

5
ibex.core
View file

@ -7,8 +7,8 @@ description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
filesets:
files_rtl:
files:
- rtl/include/ibex_defines.sv
- rtl/include/ibex_tracer_defines.sv
- rtl/ibex_defines.sv
- rtl/ibex_tracer_defines.sv
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
@ -28,7 +28,6 @@ filesets:
# - rtl/ibex_register_file.sv # ASIC
- rtl/ibex_register_file_ff.sv # FPGA
- rtl/ibex_core.sv
- rtl/include/ibex_config.sv: { is_include_file: true }
file_type: systemVerilogSource
targets:

2
ibex_tracer.core
View file

@ -9,7 +9,7 @@ filesets:
depend:
- lowrisc:ibex:ibex
files:
- rtl/include/ibex_tracer_defines.sv
- rtl/ibex_tracer_defines.sv
- rtl/ibex_tracer.sv
file_type: systemVerilogSource

2
rtl/ibex_alu.sv
View file

@ -18,8 +18,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Arithmetic logic unit
*/

2
rtl/ibex_controller.sv
View file

@ -20,8 +20,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Main CPU controller of the processor
*/

4
rtl/ibex_core.f
View file

@ -1,5 +1,5 @@
include/ibex_defines.sv
include/ibex_tracer_defines.sv
ibex_defines.sv
ibex_tracer_defines.sv
ibex_alu.sv
ibex_compressed_decoder.sv
ibex_controller.sv

2
rtl/ibex_core.sv
View file

@ -21,8 +21,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Top level module of the ibex RISC-V core
*/

8
rtl/ibex_cs_registers.sv
View file

@ -19,14 +19,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
`ifndef PULP_FPGA_EMUL
`ifdef SYNTHESIS
`define ASIC_SYNTHESIS
`endif
`endif
/**
* Control and Status Registers
*

2
rtl/ibex_decoder.sv
View file

@ -21,8 +21,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Instruction decoder
*/

0
rtl/include/ibex_defines.sv → rtl/ibex_defines.sv
View file

2
rtl/ibex_ex_block.sv
View file

@ -21,8 +21,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Execution stage
*

2
rtl/ibex_fetch_fifo.sv
View file

@ -13,8 +13,6 @@
// Description: Fetch fifo //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Fetch Fifo for 32 bit memory interface
*

2
rtl/ibex_id_stage.sv
View file

@ -21,8 +21,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
// Source/Destination register instruction index
`define REG_S1 19:15
`define REG_S2 24:20

2
rtl/ibex_if_stage.sv
View file

@ -20,8 +20,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Instruction Fetch Stage
*

2
rtl/ibex_load_store_unit.sv
View file

@ -20,8 +20,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* Load Store Unit
*

2
rtl/ibex_register_file.sv
View file

@ -20,8 +20,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* RISC-V register file
*

2
rtl/ibex_register_file_ff.sv
View file

@ -19,8 +19,6 @@
// //
////////////////////////////////////////////////////////////////////////////////
`include "ibex_config.sv"
/**
* RISC-V register file
*

3
rtl/ibex_tracer.sv
View file

@ -19,9 +19,6 @@
`ifndef VERILATOR
`include "ibex_config.sv"
import ibex_defines::*;
import ibex_tracer_defines::*;

0
rtl/include/ibex_tracer_defines.sv → rtl/ibex_tracer_defines.sv
View file

30
rtl/include/ibex_config.sv
View file

@ -1,30 +0,0 @@
// Copyright lowRISC contributors.
// Copyright 2017 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
////////////////////////////////////////////////////////////////////////////////
// Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch //
// //
// Additional contributions by: //
// Markus Wegmann - markus.wegmann@technokrat.ch //
// Davide Schiavone - pschiavo@iis.ee.ethz.ch //
// //
// Design Name: RISC-V config file //
// Project Name: ibex //
// Language: SystemVerilog //
// //
// Description: Configure optional simulation modules //
// //
////////////////////////////////////////////////////////////////////////////////
// Configure optional simulation modules
// no traces for synthesis, they are not synthesizable
`ifndef SYNTHESIS
`ifndef PULP_FPGA_EMUL
`define TRACE_EXECUTION
`endif
//`define SIMCHECKER
`endif
//`define CHECK_MISALIGNED

12
src_files.yml
View file

@ -1,10 +1,9 @@
ibex:
incdirs: [
include,
]
files: [
include/ibex_defines.sv,
include/ibex_tracer_defines.sv,
ibex_defines.sv,
ibex_tracer_defines.sv,
ibex_alu.sv,
ibex_compressed_decoder.sv,
ibex_controller.sv,
@ -27,11 +26,10 @@ ibex_vip_rtl:
rtl,
]
incdirs: [
include,
]
files: [
include/ibex_defines.sv,
include/ibex_tracer_defines.sv,
ibex_defines.sv,
ibex_tracer_defines.sv,
ibex_tracer.sv,
]
ibex_regfile_rtl:
@ -41,7 +39,6 @@ ibex_regfile_rtl:
gf22
]
incdirs: [
include,
]
files: [
ibex_register_file.sv,
@ -51,7 +48,6 @@ ibex_regfile_fpga:
xilinx,
]
incdirs: [
include,
]
files: [
ibex_register_file_ff.sv,