f9ad280d0c
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include' directory, since these files are not actually included. - Remove ibex_config.sv, it's mostly unused code. The remaining defines, SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should be set through command-line flags to the simulation/synthesis tools. Initial version by Nils Gräf. |
||
|---|---|---|
| doc | ||
| rtl | ||
| .gitignore | ||
| ibex.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
Ibex: RISC-V Core
Ibex is a small 32 bit RISC-V core with a 2-stage pipeline.
Ibex fully implements the RV32IMC instruction set and a small set of RISC-V privileged specifications. Ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions.
This core was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further.
Ibex is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Documentation
The Ibex documentation can be read online at ReadTheDocs.
It is also contained in the doc folder of this repository.
We highly appreciate pull requests on the documentation if you find anything wrong or outdated!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).