mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-24 22:07:43 -04:00
Make sure all inputs/outputs use _i/_o suffices
This commit is contained in:
Pirmin Vogel
Philipp Wagner
parent
5d419cbf16
commit
fde6e505df
15 changed files with 267 additions and 268 deletions
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@ -24,8 +24,8 @@
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* Main CPU controller of the processor
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* Main CPU controller of the processor
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*/
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*/
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module ibex_controller (
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module ibex_controller (
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input logic clk,
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input logic clk_i,
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input logic rst_n,
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input logic rst_ni,
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input logic fetch_enable_i, // Start the decoding
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input logic fetch_enable_i, // Start the decoding
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output logic ctrl_busy_o, // Core is busy processing instructions
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output logic ctrl_busy_o, // Core is busy processing instructions
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@ -126,7 +126,7 @@ module ibex_controller (
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// synopsys translate_off
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// synopsys translate_off
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// make sure we are called later so that we do not generate messages for
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// make sure we are called later so that we do not generate messages for
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// glitches
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// glitches
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always_ff @(negedge clk) begin
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always_ff @(negedge clk_i) begin
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// print warning in case of decoding errors
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// print warning in case of decoding errors
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if (is_decoding_o && illegal_insn_i) begin
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if (is_decoding_o && illegal_insn_i) begin
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$display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i,
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$display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i,
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@ -498,8 +498,8 @@ module ibex_controller (
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assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE;
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assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE;
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// update registers
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// update registers
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always_ff @(posedge clk, negedge rst_n) begin : UPDATE_REGS
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always_ff @(posedge clk_i, negedge rst_ni) begin : UPDATE_REGS
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if (!rst_n) begin
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if (!rst_ni) begin
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ctrl_fsm_cs <= RESET;
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ctrl_fsm_cs <= RESET;
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//jump_done_q <= 1'b0;
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//jump_done_q <= 1'b0;
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debug_mode_q <= 1'b0;
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debug_mode_q <= 1'b0;
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179
rtl/ibex_core.sv
179
rtl/ibex_core.sv
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@ -181,6 +181,8 @@ module ibex_core #(
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logic perf_jump;
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logic perf_jump;
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logic perf_branch;
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logic perf_branch;
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logic perf_tbranch;
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logic perf_tbranch;
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logic perf_load;
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logic perf_store;
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//////////////////////
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//////////////////////
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@ -225,8 +227,8 @@ module ibex_core #(
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.DM_HALT_ADDRESS ( DM_HALT_ADDRESS ),
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.DM_HALT_ADDRESS ( DM_HALT_ADDRESS ),
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.DM_EXCEPTION_ADDRESS ( DM_EXCEPTION_ADDRESS )
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.DM_EXCEPTION_ADDRESS ( DM_EXCEPTION_ADDRESS )
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) if_stage_i (
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) if_stage_i (
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.clk ( clk ),
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.clk_i ( clk ),
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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// boot address (trap vector location)
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// boot address (trap vector location)
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.boot_addr_i ( boot_addr_i ),
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.boot_addr_i ( boot_addr_i ),
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@ -279,8 +281,8 @@ module ibex_core #(
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.RV32E(RV32E),
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.RV32E(RV32E),
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.RV32M(RV32M)
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.RV32M(RV32M)
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) id_stage_i (
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) id_stage_i (
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.clk ( clk ),
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.clk_i ( clk ),
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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.test_en_i ( test_en_i ),
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.test_en_i ( test_en_i ),
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@ -385,8 +387,8 @@ module ibex_core #(
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//if you want a SLOW or FAST multiplier
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//if you want a SLOW or FAST multiplier
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.RV32M(RV32M)
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.RV32M(RV32M)
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) ex_block_i (
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) ex_block_i (
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.clk ( clk ),
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.clk_i ( clk ),
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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// Alu signals from ID stage
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// Alu signals from ID stage
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//TODO: hot encoding
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//TODO: hot encoding
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.alu_operator_i ( alu_operator_ex ),
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.alu_operator_i ( alu_operator_ex ),
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@ -417,8 +419,8 @@ module ibex_core #(
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/////////////////////
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/////////////////////
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ibex_load_store_unit load_store_unit_i (
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ibex_load_store_unit load_store_unit_i (
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.clk ( clk ),
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.clk_i ( clk ),
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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//output to data memory
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//output to data memory
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.data_req_o ( data_req_o ),
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.data_req_o ( data_req_o ),
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@ -462,121 +464,120 @@ module ibex_core #(
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// CSRs (Control and Status Registers) //
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// CSRs (Control and Status Registers) //
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/////////////////////////////////////////
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/////////////////////////////////////////
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assign csr_access = csr_access_ex;
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assign csr_wdata = alu_operand_a_ex;
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assign csr_op = csr_op_ex;
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assign csr_addr = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : 12'b0);
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assign perf_load = data_req_o & data_gnt_i & (~data_we_o);
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assign perf_store = data_req_o & data_gnt_i & data_we_o;
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ibex_cs_registers #(
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ibex_cs_registers #(
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.N_EXT_CNT ( N_EXT_PERF_COUNTERS ),
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.N_EXT_CNT ( N_EXT_PERF_COUNTERS ),
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.RV32E ( RV32E ),
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.RV32E ( RV32E ),
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.RV32M ( RV32M )
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.RV32M ( RV32M )
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) cs_registers_i (
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) cs_registers_i (
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.clk ( clk ),
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.clk_i ( clk ),
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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// Core and Cluster ID from outside
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// Core and Cluster ID from outside
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.core_id_i ( core_id_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.cluster_id_i ( cluster_id_i ),
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// boot address
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// boot address
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.boot_addr_i ( boot_addr_i ),
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.boot_addr_i ( boot_addr_i ),
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// Interface to CSRs (SRAM like)
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// Interface to CSRs (SRAM like)
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.csr_access_i ( csr_access ),
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.csr_access_i ( csr_access ),
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.csr_addr_i ( csr_addr ),
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.csr_addr_i ( csr_addr ),
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.csr_wdata_i ( csr_wdata ),
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.csr_wdata_i ( csr_wdata ),
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.csr_op_i ( csr_op ),
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.csr_op_i ( csr_op ),
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.csr_rdata_o ( csr_rdata ),
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.csr_rdata_o ( csr_rdata ),
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// Interrupt related control signals
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// Interrupt related control signals
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.m_irq_enable_o ( m_irq_enable ),
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.m_irq_enable_o ( m_irq_enable ),
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.mepc_o ( mepc ),
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.mepc_o ( mepc ),
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// debug
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// debug
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.debug_cause_i ( debug_cause ),
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.debug_cause_i ( debug_cause ),
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.debug_csr_save_i ( debug_csr_save ),
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.debug_csr_save_i ( debug_csr_save ),
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.depc_o ( depc ),
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.depc_o ( depc ),
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.debug_single_step_o ( debug_single_step ),
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.debug_single_step_o ( debug_single_step ),
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.debug_ebreakm_o ( debug_ebreakm ),
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.debug_ebreakm_o ( debug_ebreakm ),
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.pc_if_i ( pc_if ),
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.pc_if_i ( pc_if ),
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.pc_id_i ( pc_id ),
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.pc_id_i ( pc_id ),
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.csr_save_if_i ( csr_save_if ),
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.csr_save_if_i ( csr_save_if ),
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.csr_save_id_i ( csr_save_id ),
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.csr_save_id_i ( csr_save_id ),
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.csr_restore_mret_i ( csr_restore_mret_id ),
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.csr_restore_mret_i ( csr_restore_mret_id ),
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.csr_restore_dret_i ( csr_restore_dret_id ),
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.csr_restore_dret_i ( csr_restore_dret_id ),
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.csr_cause_i ( csr_cause ),
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.csr_cause_i ( csr_cause ),
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.csr_save_cause_i ( csr_save_cause ),
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.csr_save_cause_i ( csr_save_cause ),
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// performance counter related signals
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// performance counter related signals
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.if_valid_i ( if_valid ),
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.if_valid_i ( if_valid ),
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.id_valid_i ( id_valid ),
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.id_valid_i ( id_valid ),
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.is_compressed_i ( is_compressed_id ),
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.is_compressed_i ( is_compressed_id ),
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.is_decoding_i ( is_decoding ),
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.is_decoding_i ( is_decoding ),
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.imiss_i ( perf_imiss ),
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.imiss_i ( perf_imiss ),
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.pc_set_i ( pc_set ),
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.pc_set_i ( pc_set ),
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.jump_i ( perf_jump ),
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.jump_i ( perf_jump ),
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.branch_i ( perf_branch ),
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.branch_i ( perf_branch ),
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.branch_taken_i ( perf_tbranch ),
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.branch_taken_i ( perf_tbranch ),
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.mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ),
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.mem_load_i ( perf_load ),
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.mem_store_i ( data_req_o & data_gnt_i & data_we_o ),
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.mem_store_i ( perf_store ),
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.ext_counters_i ( ext_perf_counters_i )
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.ext_counters_i ( ext_perf_counters_i )
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);
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);
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// CSR access
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assign csr_access = csr_access_ex;
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assign csr_wdata = alu_operand_a_ex;
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assign csr_op = csr_op_ex;
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assign csr_addr = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : 12'b0);
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`ifndef VERILATOR
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`ifndef VERILATOR
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`ifdef TRACE_EXECUTION
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`ifdef TRACE_EXECUTION
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ibex_tracer ibex_tracer_i (
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ibex_tracer ibex_tracer_i (
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.clk ( clk_i ), // always-running clock for tracing
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.clk_i ( clk_i ), // always-running clock for tracing
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.rst_n ( rst_ni ),
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.rst_ni ( rst_ni ),
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.fetch_enable ( fetch_enable_i ),
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.fetch_enable_i ( fetch_enable_i ),
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.core_id ( core_id_i ),
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.core_id_i ( core_id_i ),
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.cluster_id ( cluster_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.pc ( id_stage_i.pc_id_i ),
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.pc_i ( id_stage_i.pc_id_i ),
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.instr ( id_stage_i.instr ),
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.instr_i ( id_stage_i.instr ),
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.compressed ( id_stage_i.is_compressed_i ),
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.compressed_i ( id_stage_i.is_compressed_i ),
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.id_valid ( id_stage_i.id_valid_o ),
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.id_valid_i ( id_stage_i.id_valid_o ),
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.is_decoding ( id_stage_i.is_decoding_o ),
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.is_decoding_i ( id_stage_i.is_decoding_o ),
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.is_branch ( id_stage_i.branch_in_id ),
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.is_branch_i ( id_stage_i.branch_in_id ),
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.branch_taken ( id_stage_i.branch_set_q ),
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.branch_taken_i ( id_stage_i.branch_set_q ),
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.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
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.pipe_flush_i ( id_stage_i.controller_i.pipe_flush_i ),
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.mret_insn ( id_stage_i.controller_i.mret_insn_i ),
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.mret_insn_i ( id_stage_i.controller_i.mret_insn_i ),
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.dret_insn ( id_stage_i.controller_i.dret_insn_i ),
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.dret_insn_i ( id_stage_i.controller_i.dret_insn_i ),
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.ecall_insn ( id_stage_i.controller_i.ecall_insn_i ),
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.ecall_insn_i ( id_stage_i.controller_i.ecall_insn_i ),
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.ebrk_insn ( id_stage_i.controller_i.ebrk_insn_i ),
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.ebrk_insn_i ( id_stage_i.controller_i.ebrk_insn_i ),
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.csr_status ( id_stage_i.controller_i.csr_status_i ),
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.csr_status_i ( id_stage_i.controller_i.csr_status_i ),
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.rs1_value ( id_stage_i.operand_a_fw_id ),
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.rs1_value_i ( id_stage_i.operand_a_fw_id ),
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.rs2_value ( id_stage_i.operand_b_fw_id ),
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.rs2_value_i ( id_stage_i.operand_b_fw_id ),
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.lsu_value ( data_wdata_ex ),
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.lsu_value_i ( data_wdata_ex ),
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.ex_reg_addr ( id_stage_i.regfile_waddr_mux ),
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.ex_reg_addr_i ( id_stage_i.regfile_waddr_mux ),
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.ex_reg_we ( id_stage_i.regfile_we_mux ),
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.ex_reg_we_i ( id_stage_i.regfile_we_mux ),
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.ex_reg_wdata ( id_stage_i.regfile_wdata_mux ),
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.ex_reg_wdata_i ( id_stage_i.regfile_wdata_mux ),
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.data_valid_lsu ( data_valid_lsu ),
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.data_valid_lsu_i ( data_valid_lsu ),
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.ex_data_addr ( data_addr_o ),
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.ex_data_addr_i ( data_addr_o ),
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.ex_data_req ( data_req_o ),
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.ex_data_req_i ( data_req_o ),
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.ex_data_gnt ( data_gnt_i ),
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.ex_data_gnt_i ( data_gnt_i ),
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.ex_data_we ( data_we_o ),
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.ex_data_we_i ( data_we_o ),
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.ex_data_wdata ( data_wdata_o ),
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.ex_data_wdata_i ( data_wdata_o ),
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.lsu_reg_wdata ( regfile_wdata_lsu ),
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.lsu_reg_wdata_i ( regfile_wdata_lsu ),
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.imm_i_type ( id_stage_i.imm_i_type ),
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.imm_i_type_i ( id_stage_i.imm_i_type ),
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.imm_s_type ( id_stage_i.imm_s_type ),
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.imm_s_type_i ( id_stage_i.imm_s_type ),
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.imm_b_type ( id_stage_i.imm_b_type ),
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.imm_b_type_i ( id_stage_i.imm_b_type ),
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.imm_u_type ( id_stage_i.imm_u_type ),
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.imm_u_type_i ( id_stage_i.imm_u_type ),
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.imm_j_type ( id_stage_i.imm_j_type ),
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.imm_j_type_i ( id_stage_i.imm_j_type ),
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.zimm_rs1_type ( id_stage_i.zimm_rs1_type )
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.zimm_rs1_type_i ( id_stage_i.zimm_rs1_type )
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);
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);
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`endif
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`endif
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`endif
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`endif
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@ -31,8 +31,8 @@ module ibex_cs_registers #(
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parameter bit RV32M = 0
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parameter bit RV32M = 0
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) (
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) (
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// Clock and Reset
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// Clock and Reset
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input logic clk,
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input logic clk_i,
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input logic rst_n,
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input logic rst_ni,
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// Core and Cluster ID
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// Core and Cluster ID
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input logic [3:0] core_id_i,
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input logic [3:0] core_id_i,
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@ -69,7 +69,6 @@ module ibex_cs_registers #(
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input ibex_defines::exc_cause_e csr_cause_i,
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input ibex_defines::exc_cause_e csr_cause_i,
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input logic csr_save_cause_i,
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input logic csr_save_cause_i,
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// Performance Counters
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// Performance Counters
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input logic if_valid_i, // IF stage gives a new instruction
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input logic if_valid_i, // IF stage gives a new instruction
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input logic id_valid_i, // ID stage is done
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input logic id_valid_i, // ID stage is done
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@ -360,8 +359,8 @@ module ibex_cs_registers #(
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assign debug_ebreakm_o = dcsr_q.ebreakm;
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assign debug_ebreakm_o = dcsr_q.ebreakm;
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// actual registers
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// actual registers
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always_ff @(posedge clk, negedge rst_n) begin
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always_ff @(posedge clk_i, negedge rst_ni) begin
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if (!rst_n) begin
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if (!rst_ni) begin
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mstatus_q <= '{
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mstatus_q <= '{
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mie: 1'b0,
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mie: 1'b0,
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mpie: 1'b0,
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mpie: 1'b0,
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@ -533,8 +532,8 @@ module ibex_cs_registers #(
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end
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end
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// Performance Counter Registers
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// Performance Counter Registers
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always_ff @(posedge clk, negedge rst_n) begin
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always_ff @(posedge clk_i, negedge rst_ni) begin
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if (!rst_n) begin
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if (!rst_ni) begin
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PCER_q <= '0;
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PCER_q <= '0;
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PCMR_q <= 2'h3;
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PCMR_q <= 2'h3;
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@ -29,8 +29,8 @@
|
||||||
module ibex_ex_block #(
|
module ibex_ex_block #(
|
||||||
parameter bit RV32M = 1
|
parameter bit RV32M = 1
|
||||||
) (
|
) (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
// ALU signals from ID stage
|
// ALU signals from ID stage
|
||||||
input ibex_defines::alu_op_e alu_operator_i,
|
input ibex_defines::alu_op_e alu_operator_i,
|
||||||
|
|
@ -114,8 +114,8 @@ module ibex_ex_block #(
|
||||||
|
|
||||||
if (!MULT_TYPE) begin : gen_multdiv_slow
|
if (!MULT_TYPE) begin : gen_multdiv_slow
|
||||||
ibex_multdiv_slow multdiv_i (
|
ibex_multdiv_slow multdiv_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
.mult_en_i ( mult_en_i ),
|
.mult_en_i ( mult_en_i ),
|
||||||
.div_en_i ( div_en_i ),
|
.div_en_i ( div_en_i ),
|
||||||
.operator_i ( multdiv_operator_i ),
|
.operator_i ( multdiv_operator_i ),
|
||||||
|
|
@ -132,8 +132,8 @@ module ibex_ex_block #(
|
||||||
);
|
);
|
||||||
end else begin: gen_multdiv_fast
|
end else begin: gen_multdiv_fast
|
||||||
ibex_multdiv_fast multdiv_i (
|
ibex_multdiv_fast multdiv_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
.mult_en_i ( mult_en_i ),
|
.mult_en_i ( mult_en_i ),
|
||||||
.div_en_i ( div_en_i ),
|
.div_en_i ( div_en_i ),
|
||||||
.operator_i ( multdiv_operator_i ),
|
.operator_i ( multdiv_operator_i ),
|
||||||
|
|
|
||||||
|
|
@ -21,8 +21,8 @@
|
||||||
* this cycle already.
|
* this cycle already.
|
||||||
*/
|
*/
|
||||||
module ibex_fetch_fifo (
|
module ibex_fetch_fifo (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
// control signals
|
// control signals
|
||||||
input logic clear_i, // clears the contents of the fifo
|
input logic clear_i, // clears the contents of the fifo
|
||||||
|
|
@ -182,8 +182,8 @@ module ibex_fetch_fifo (
|
||||||
// registers //
|
// registers //
|
||||||
///////////////
|
///////////////
|
||||||
|
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
addr_Q <= '{default: '0};
|
addr_Q <= '{default: '0};
|
||||||
rdata_Q <= '{default: '0};
|
rdata_Q <= '{default: '0};
|
||||||
valid_Q <= '0;
|
valid_Q <= '0;
|
||||||
|
|
@ -205,6 +205,6 @@ module ibex_fetch_fifo (
|
||||||
////////////////
|
////////////////
|
||||||
`ifndef VERILATOR
|
`ifndef VERILATOR
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) );
|
@(posedge clk_i) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) );
|
||||||
`endif
|
`endif
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -36,8 +36,8 @@ module ibex_id_stage #(
|
||||||
parameter bit RV32M = 1,
|
parameter bit RV32M = 1,
|
||||||
parameter bit RV32E = 0
|
parameter bit RV32E = 0
|
||||||
) (
|
) (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
input logic test_en_i,
|
input logic test_en_i,
|
||||||
|
|
||||||
|
|
@ -328,8 +328,8 @@ module ibex_id_stage #(
|
||||||
end
|
end
|
||||||
|
|
||||||
ibex_register_file #( .RV32E(RV32E)) registers_i (
|
ibex_register_file #( .RV32E(RV32E)) registers_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
|
|
||||||
.test_en_i ( test_en_i ),
|
.test_en_i ( test_en_i ),
|
||||||
|
|
||||||
|
|
@ -406,8 +406,8 @@ module ibex_id_stage #(
|
||||||
////////////////
|
////////////////
|
||||||
|
|
||||||
ibex_controller controller_i (
|
ibex_controller controller_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
|
|
||||||
.fetch_enable_i ( fetch_enable_i ),
|
.fetch_enable_i ( fetch_enable_i ),
|
||||||
.ctrl_busy_o ( ctrl_busy_o ),
|
.ctrl_busy_o ( ctrl_busy_o ),
|
||||||
|
|
@ -492,8 +492,8 @@ module ibex_id_stage #(
|
||||||
//////////////////////////
|
//////////////////////////
|
||||||
|
|
||||||
ibex_int_controller int_controller_i (
|
ibex_int_controller int_controller_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
|
|
||||||
// to controller
|
// to controller
|
||||||
.irq_req_ctrl_o ( irq_req_ctrl ),
|
.irq_req_ctrl_o ( irq_req_ctrl ),
|
||||||
|
|
@ -541,8 +541,8 @@ module ibex_id_stage #(
|
||||||
////////////////////////////////
|
////////////////////////////////
|
||||||
// ID-EX/WB Pipeline Register //
|
// ID-EX/WB Pipeline Register //
|
||||||
////////////////////////////////
|
////////////////////////////////
|
||||||
always_ff @(posedge clk, negedge rst_n) begin : EX_WB_Pipeline_Register
|
always_ff @(posedge clk_i, negedge rst_ni) begin : EX_WB_Pipeline_Register
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
id_wb_fsm_cs <= IDLE;
|
id_wb_fsm_cs <= IDLE;
|
||||||
branch_set_q <= 1'b0;
|
branch_set_q <= 1'b0;
|
||||||
end else begin
|
end else begin
|
||||||
|
|
@ -645,22 +645,22 @@ module ibex_id_stage #(
|
||||||
`ifndef VERILATOR
|
`ifndef VERILATOR
|
||||||
// make sure that branch decision is valid when jumping
|
// make sure that branch decision is valid when jumping
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (branch_decision_i !== 1'bx || branch_in_id == 1'b0) ) else begin
|
@(posedge clk_i) (branch_decision_i !== 1'bx || branch_in_id == 1'b0) ) else begin
|
||||||
$display("Branch decision is X"); $stop; end
|
$display("Branch decision is X"); $stop; end
|
||||||
|
|
||||||
`ifdef CHECK_MISALIGNED
|
`ifdef CHECK_MISALIGNED
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (~data_misaligned_i) ) else $display("Misaligned memory access at %x",pc_id_i);
|
@(posedge clk_i) (~data_misaligned_i) ) else $display("Misaligned memory access at %x",pc_id_i);
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// the instruction delivered to the ID stage should always be valid
|
// the instruction delivered to the ID stage should always be valid
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (instr_valid_i & (~illegal_c_insn_i)) |-> (!$isunknown(instr_rdata_i)) ) else
|
@(posedge clk_i) (instr_valid_i & (~illegal_c_insn_i)) |-> (!$isunknown(instr_rdata_i)) ) else
|
||||||
$display("Instruction is valid, but has at least one X");
|
$display("Instruction is valid, but has at least one X");
|
||||||
|
|
||||||
// make sure multicycles enable signals are unique
|
// make sure multicycles enable signals are unique
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) ~(data_req_ex_o & multdiv_int_en )) else
|
@(posedge clk_i) ~(data_req_ex_o & multdiv_int_en )) else
|
||||||
$display("Multicycles enable signals are not unique");
|
$display("Multicycles enable signals are not unique");
|
||||||
|
|
||||||
`endif
|
`endif
|
||||||
|
|
|
||||||
|
|
@ -30,8 +30,8 @@ module ibex_if_stage #(
|
||||||
parameter DM_HALT_ADDRESS = 32'h1A110800,
|
parameter DM_HALT_ADDRESS = 32'h1A110800,
|
||||||
parameter DM_EXCEPTION_ADDRESS = 32'h1A110808
|
parameter DM_EXCEPTION_ADDRESS = 32'h1A110808
|
||||||
) (
|
) (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
// the boot address is used to calculate the exception offsets
|
// the boot address is used to calculate the exception offsets
|
||||||
input logic [31:0] boot_addr_i,
|
input logic [31:0] boot_addr_i,
|
||||||
// instruction request control
|
// instruction request control
|
||||||
|
|
@ -129,8 +129,8 @@ module ibex_if_stage #(
|
||||||
|
|
||||||
// prefetch buffer, caches a fixed number of instructions
|
// prefetch buffer, caches a fixed number of instructions
|
||||||
ibex_prefetch_buffer prefetch_buffer_i (
|
ibex_prefetch_buffer prefetch_buffer_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
|
|
||||||
.req_i ( req_i ),
|
.req_i ( req_i ),
|
||||||
|
|
||||||
|
|
@ -155,8 +155,8 @@ module ibex_if_stage #(
|
||||||
|
|
||||||
|
|
||||||
// offset initialization state
|
// offset initialization state
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
offset_in_init_q <= 1'b1;
|
offset_in_init_q <= 1'b1;
|
||||||
end else begin
|
end else begin
|
||||||
offset_in_init_q <= offset_in_init_d;
|
offset_in_init_q <= offset_in_init_d;
|
||||||
|
|
@ -219,8 +219,8 @@ module ibex_if_stage #(
|
||||||
);
|
);
|
||||||
|
|
||||||
// IF-ID pipeline registers, frozen when the ID stage is stalled
|
// IF-ID pipeline registers, frozen when the ID stage is stalled
|
||||||
always_ff @(posedge clk, negedge rst_n) begin : IF_ID_PIPE_REGISTERS
|
always_ff @(posedge clk_i, negedge rst_ni) begin : IF_ID_PIPE_REGISTERS
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
instr_valid_id_o <= 1'b0;
|
instr_valid_id_o <= 1'b0;
|
||||||
instr_rdata_id_o <= '0;
|
instr_rdata_id_o <= '0;
|
||||||
illegal_c_insn_id_o <= 1'b0;
|
illegal_c_insn_id_o <= 1'b0;
|
||||||
|
|
@ -248,12 +248,12 @@ module ibex_if_stage #(
|
||||||
`ifndef VERILATOR
|
`ifndef VERILATOR
|
||||||
// the boot address needs to be aligned to 256 bytes
|
// the boot address needs to be aligned to 256 bytes
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (boot_addr_i[7:0] == 8'h00) )
|
@(posedge clk_i) (boot_addr_i[7:0] == 8'h00) )
|
||||||
else $error("The provided boot address is not aligned to 256 bytes");
|
else $error("The provided boot address is not aligned to 256 bytes");
|
||||||
|
|
||||||
// there should never be a grant when there is no request
|
// there should never be a grant when there is no request
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) (instr_gnt_i) |-> (instr_req_o) )
|
@(posedge clk_i) (instr_gnt_i) |-> (instr_req_o) )
|
||||||
else $warning("There was a grant without a request");
|
else $warning("There was a grant without a request");
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -20,8 +20,8 @@
|
||||||
* Interrupt Controller
|
* Interrupt Controller
|
||||||
*/
|
*/
|
||||||
module ibex_int_controller (
|
module ibex_int_controller (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
// irq_req for controller
|
// irq_req for controller
|
||||||
output logic irq_req_ctrl_o,
|
output logic irq_req_ctrl_o,
|
||||||
|
|
@ -50,8 +50,8 @@ module ibex_int_controller (
|
||||||
assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING;
|
assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING;
|
||||||
assign irq_id_ctrl_o = irq_id_q;
|
assign irq_id_ctrl_o = irq_id_q;
|
||||||
|
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
irq_id_q <= '0;
|
irq_id_q <= '0;
|
||||||
exc_ctrl_cs <= IDLE;
|
exc_ctrl_cs <= IDLE;
|
||||||
end else begin
|
end else begin
|
||||||
|
|
|
||||||
|
|
@ -27,8 +27,8 @@
|
||||||
* and to align bytes and halfwords.
|
* and to align bytes and halfwords.
|
||||||
*/
|
*/
|
||||||
module ibex_load_store_unit (
|
module ibex_load_store_unit (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
// output to data memory
|
// output to data memory
|
||||||
output logic data_req_o,
|
output logic data_req_o,
|
||||||
|
|
@ -157,8 +157,8 @@ module ibex_load_store_unit (
|
||||||
|
|
||||||
|
|
||||||
// FF for rdata alignment and sign-extension
|
// FF for rdata alignment and sign-extension
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
data_type_q <= 2'h0;
|
data_type_q <= 2'h0;
|
||||||
rdata_offset_q <= 2'h0;
|
rdata_offset_q <= 2'h0;
|
||||||
data_sign_ext_q <= 1'b0;
|
data_sign_ext_q <= 1'b0;
|
||||||
|
|
@ -277,8 +277,8 @@ module ibex_load_store_unit (
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
CS <= IDLE;
|
CS <= IDLE;
|
||||||
rdata_q <= '0;
|
rdata_q <= '0;
|
||||||
data_misaligned_q <= '0;
|
data_misaligned_q <= '0;
|
||||||
|
|
@ -451,16 +451,15 @@ module ibex_load_store_unit (
|
||||||
// i.e. it should not be possible to get a grant without an rvalid for the
|
// i.e. it should not be possible to get a grant without an rvalid for the
|
||||||
// last request
|
// last request
|
||||||
assert property (
|
assert property (
|
||||||
@(posedge clk) ((CS == WAIT_RVALID) && (data_gnt_i == 1'b1)) |-> (data_rvalid_i == 1'b1) );
|
@(posedge clk_i) ((CS == WAIT_RVALID) && (data_gnt_i == 1'b1)) |-> (data_rvalid_i == 1'b1) );
|
||||||
|
|
||||||
// there should be no rvalid when we are in IDLE
|
// there should be no rvalid when we are in IDLE
|
||||||
assert property (
|
assert property ( @(posedge clk_i) (CS == IDLE) |-> (data_rvalid_i == 1'b0) );
|
||||||
@(posedge clk) (CS == IDLE) |-> (data_rvalid_i == 1'b0) );
|
|
||||||
|
|
||||||
// assert that errors are only sent at the same time as grant
|
// assert that errors are only sent at the same time as grant
|
||||||
assert property ( @(posedge clk) (data_err_i) |-> (data_gnt_i) );
|
assert property ( @(posedge clk_i) (data_err_i) |-> (data_gnt_i) );
|
||||||
|
|
||||||
// assert that the address does not contain X when request is sent
|
// assert that the address does not contain X when request is sent
|
||||||
assert property ( @(posedge clk) (data_req_o) |-> (!$isunknown(data_addr_o)) );
|
assert property ( @(posedge clk_i) (data_req_o) |-> (!$isunknown(data_addr_o)) );
|
||||||
`endif
|
`endif
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -24,8 +24,8 @@
|
||||||
* 16x16 kernel multiplier and Long Division
|
* 16x16 kernel multiplier and Long Division
|
||||||
*/
|
*/
|
||||||
module ibex_multdiv_fast (
|
module ibex_multdiv_fast (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
input logic mult_en_i,
|
input logic mult_en_i,
|
||||||
input logic div_en_i,
|
input logic div_en_i,
|
||||||
input ibex_defines::md_op_e operator_i,
|
input ibex_defines::md_op_e operator_i,
|
||||||
|
|
@ -79,8 +79,8 @@ module ibex_multdiv_fast (
|
||||||
logic [32:0] res_adder_h;
|
logic [32:0] res_adder_h;
|
||||||
logic mult_is_ready;
|
logic mult_is_ready;
|
||||||
|
|
||||||
always_ff @(posedge clk or negedge rst_n) begin : proc_mult_state_q
|
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_mult_state_q
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
mult_state_q <= ALBL;
|
mult_state_q <= ALBL;
|
||||||
mac_res_q <= '0;
|
mac_res_q <= '0;
|
||||||
div_counter_q <= '0;
|
div_counter_q <= '0;
|
||||||
|
|
|
||||||
|
|
@ -21,8 +21,8 @@
|
||||||
* Baugh-Wooley multiplier and Long Division
|
* Baugh-Wooley multiplier and Long Division
|
||||||
*/
|
*/
|
||||||
module ibex_multdiv_slow (
|
module ibex_multdiv_slow (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
input logic mult_en_i,
|
input logic mult_en_i,
|
||||||
input logic div_en_i,
|
input logic div_en_i,
|
||||||
input ibex_defines::md_op_e operator_i,
|
input ibex_defines::md_op_e operator_i,
|
||||||
|
|
@ -155,8 +155,8 @@ module ibex_multdiv_slow (
|
||||||
assign div_change_sign = sign_a ^ sign_b;
|
assign div_change_sign = sign_a ^ sign_b;
|
||||||
assign rem_change_sign = sign_a;
|
assign rem_change_sign = sign_a;
|
||||||
|
|
||||||
always_ff @(posedge clk or negedge rst_n) begin : proc_multdiv_state_q
|
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_multdiv_state_q
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
multdiv_state_q <= 5'h0;
|
multdiv_state_q <= 5'h0;
|
||||||
accum_window_q <= 33'h0;
|
accum_window_q <= 33'h0;
|
||||||
op_b_shift_q <= 33'h0;
|
op_b_shift_q <= 33'h0;
|
||||||
|
|
|
||||||
|
|
@ -21,8 +21,8 @@
|
||||||
* paths to the instruction cache.
|
* paths to the instruction cache.
|
||||||
*/
|
*/
|
||||||
module ibex_prefetch_buffer (
|
module ibex_prefetch_buffer (
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
input logic req_i,
|
input logic req_i,
|
||||||
|
|
||||||
|
|
@ -71,8 +71,8 @@ module ibex_prefetch_buffer (
|
||||||
//////////////////////////////////////////////
|
//////////////////////////////////////////////
|
||||||
|
|
||||||
ibex_fetch_fifo fifo_i (
|
ibex_fetch_fifo fifo_i (
|
||||||
.clk ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.rst_n ( rst_n ),
|
.rst_ni ( rst_ni ),
|
||||||
|
|
||||||
.clear_i ( fifo_clear ),
|
.clear_i ( fifo_clear ),
|
||||||
|
|
||||||
|
|
@ -210,8 +210,8 @@ module ibex_prefetch_buffer (
|
||||||
// Registers //
|
// Registers //
|
||||||
///////////////
|
///////////////
|
||||||
|
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
CS <= IDLE;
|
CS <= IDLE;
|
||||||
instr_addr_q <= '0;
|
instr_addr_q <= '0;
|
||||||
end else begin
|
end else begin
|
||||||
|
|
|
||||||
|
|
@ -32,8 +32,8 @@ module ibex_register_file #(
|
||||||
parameter DATA_WIDTH = 32
|
parameter DATA_WIDTH = 32
|
||||||
) (
|
) (
|
||||||
// Clock and Reset
|
// Clock and Reset
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
input logic test_en_i,
|
input logic test_en_i,
|
||||||
|
|
||||||
|
|
@ -84,15 +84,15 @@ module ibex_register_file #(
|
||||||
///////////////////////////////
|
///////////////////////////////
|
||||||
|
|
||||||
prim_clock_gating CG_WE_GLOBAL (
|
prim_clock_gating CG_WE_GLOBAL (
|
||||||
.clk_i ( clk ),
|
.clk_i ( clk_i ),
|
||||||
.en_i ( we_a_i ),
|
.en_i ( we_a_i ),
|
||||||
.test_en_i ( test_en_i ),
|
.test_en_i ( test_en_i ),
|
||||||
.clk_o ( clk_int )
|
.clk_o ( clk_int )
|
||||||
);
|
);
|
||||||
|
|
||||||
// use clk_int here, since otherwise we don't want to write anything anyway
|
// use clk_int here, since otherwise we don't want to write anything anyway
|
||||||
always_ff @(posedge clk_int, negedge rst_n) begin : sample_waddr
|
always_ff @(posedge clk_int, negedge rst_ni) begin : sample_waddr
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
wdata_a_q <= '0;
|
wdata_a_q <= '0;
|
||||||
end else begin
|
end else begin
|
||||||
if (we_a_i) begin
|
if (we_a_i) begin
|
||||||
|
|
|
||||||
|
|
@ -30,8 +30,8 @@ module ibex_register_file #(
|
||||||
parameter DATA_WIDTH = 32
|
parameter DATA_WIDTH = 32
|
||||||
) (
|
) (
|
||||||
// Clock and Reset
|
// Clock and Reset
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
input logic test_en_i,
|
input logic test_en_i,
|
||||||
|
|
||||||
|
|
@ -65,8 +65,8 @@ module ibex_register_file #(
|
||||||
end
|
end
|
||||||
|
|
||||||
// loop from 1 to NUM_WORDS-1 as R0 is nil
|
// loop from 1 to NUM_WORDS-1 as R0 is nil
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
rf_reg_tmp <= '{default:'0};
|
rf_reg_tmp <= '{default:'0};
|
||||||
end else begin
|
end else begin
|
||||||
for (int r = 1; r < NUM_WORDS; r++) begin
|
for (int r = 1; r < NUM_WORDS; r++) begin
|
||||||
|
|
|
||||||
|
|
@ -36,48 +36,48 @@ module ibex_tracer #(
|
||||||
parameter REG_ADDR_WIDTH = 5
|
parameter REG_ADDR_WIDTH = 5
|
||||||
) (
|
) (
|
||||||
// Clock and Reset
|
// Clock and Reset
|
||||||
input logic clk,
|
input logic clk_i,
|
||||||
input logic rst_n,
|
input logic rst_ni,
|
||||||
|
|
||||||
input logic fetch_enable,
|
input logic fetch_enable_i,
|
||||||
input logic [3:0] core_id,
|
input logic [3:0] core_id_i,
|
||||||
input logic [5:0] cluster_id,
|
input logic [5:0] cluster_id_i,
|
||||||
|
|
||||||
input logic [31:0] pc,
|
input logic [31:0] pc_i,
|
||||||
input logic [31:0] instr,
|
input logic [31:0] instr_i,
|
||||||
input logic compressed,
|
input logic compressed_i,
|
||||||
input logic id_valid,
|
input logic id_valid_i,
|
||||||
input logic is_decoding,
|
input logic is_decoding_i,
|
||||||
input logic is_branch,
|
input logic is_branch_i,
|
||||||
input logic branch_taken,
|
input logic branch_taken_i,
|
||||||
input logic pipe_flush,
|
input logic pipe_flush_i,
|
||||||
input logic mret_insn,
|
input logic mret_insn_i,
|
||||||
input logic dret_insn,
|
input logic dret_insn_i,
|
||||||
input logic ecall_insn,
|
input logic ecall_insn_i,
|
||||||
input logic ebrk_insn,
|
input logic ebrk_insn_i,
|
||||||
input logic csr_status,
|
input logic csr_status_i,
|
||||||
input logic [31:0] rs1_value,
|
input logic [31:0] rs1_value_i,
|
||||||
input logic [31:0] rs2_value,
|
input logic [31:0] rs2_value_i,
|
||||||
input logic [31:0] lsu_value,
|
input logic [31:0] lsu_value_i,
|
||||||
|
|
||||||
input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr,
|
input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr_i,
|
||||||
input logic ex_reg_we,
|
input logic ex_reg_we_i,
|
||||||
input logic [31:0] ex_reg_wdata,
|
input logic [31:0] ex_reg_wdata_i,
|
||||||
input logic data_valid_lsu,
|
input logic data_valid_lsu_i,
|
||||||
input logic ex_data_req,
|
input logic ex_data_req_i,
|
||||||
input logic ex_data_gnt,
|
input logic ex_data_gnt_i,
|
||||||
input logic ex_data_we,
|
input logic ex_data_we_i,
|
||||||
input logic [31:0] ex_data_addr,
|
input logic [31:0] ex_data_addr_i,
|
||||||
input logic [31:0] ex_data_wdata,
|
input logic [31:0] ex_data_wdata_i,
|
||||||
|
|
||||||
input logic [31:0] lsu_reg_wdata,
|
input logic [31:0] lsu_reg_wdata_i,
|
||||||
|
|
||||||
input logic [31:0] imm_i_type,
|
input logic [31:0] imm_i_type_i,
|
||||||
input logic [31:0] imm_s_type,
|
input logic [31:0] imm_s_type_i,
|
||||||
input logic [31:0] imm_b_type,
|
input logic [31:0] imm_b_type_i,
|
||||||
input logic [31:0] imm_u_type,
|
input logic [31:0] imm_u_type_i,
|
||||||
input logic [31:0] imm_j_type,
|
input logic [31:0] imm_j_type_i,
|
||||||
input logic [31:0] zimm_rs1_type
|
input logic [31:0] zimm_rs1_type_i
|
||||||
);
|
);
|
||||||
|
|
||||||
integer f;
|
integer f;
|
||||||
|
|
@ -130,8 +130,8 @@ module ibex_tracer #(
|
||||||
begin
|
begin
|
||||||
$fwrite(f, "%t %15d %h %h %-36s", simtime,
|
$fwrite(f, "%t %15d %h %h %-36s", simtime,
|
||||||
cycles,
|
cycles,
|
||||||
pc,
|
pc_i,
|
||||||
instr,
|
instr_i,
|
||||||
str);
|
str);
|
||||||
|
|
||||||
foreach(regs_write[i]) begin
|
foreach(regs_write[i]) begin
|
||||||
|
|
@ -164,8 +164,8 @@ module ibex_tracer #(
|
||||||
|
|
||||||
function void printRInstr(input string mnemonic);
|
function void printRInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
regs_read.push_back('{rs2, rs2_value});
|
regs_read.push_back('{rs2, rs2_value_i});
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
|
str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
|
||||||
end
|
end
|
||||||
|
|
@ -173,54 +173,54 @@ module ibex_tracer #(
|
||||||
|
|
||||||
function void printIInstr(input string mnemonic);
|
function void printIInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type));
|
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type_i));
|
||||||
end
|
end
|
||||||
endfunction // printIInstr
|
endfunction // printIInstr
|
||||||
|
|
||||||
function void printIuInstr(input string mnemonic);
|
function void printIuInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type);
|
str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type_i);
|
||||||
end
|
end
|
||||||
endfunction // printIuInstr
|
endfunction // printIuInstr
|
||||||
|
|
||||||
function void printUInstr(input string mnemonic);
|
function void printUInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000});
|
str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type_i[31:12], 12'h000});
|
||||||
end
|
end
|
||||||
endfunction // printUInstr
|
endfunction // printUInstr
|
||||||
|
|
||||||
function void printUJInstr(input string mnemonic);
|
function void printUJInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_j_type));
|
str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_j_type_i));
|
||||||
end
|
end
|
||||||
endfunction // printUJInstr
|
endfunction // printUJInstr
|
||||||
|
|
||||||
function void printSBInstr(input string mnemonic);
|
function void printSBInstr(input string mnemonic);
|
||||||
begin
|
begin
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
regs_read.push_back('{rs2, rs2_value});
|
regs_read.push_back('{rs2, rs2_value_i});
|
||||||
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_b_type));
|
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_b_type_i));
|
||||||
end
|
end
|
||||||
endfunction // printSBInstr
|
endfunction // printSBInstr
|
||||||
|
|
||||||
function void printCSRInstr(input string mnemonic);
|
function void printCSRInstr(input string mnemonic);
|
||||||
logic [11:0] csr;
|
logic [11:0] csr;
|
||||||
begin
|
begin
|
||||||
csr = instr[31:20];
|
csr = instr_i[31:20];
|
||||||
|
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
|
|
||||||
if (!instr[14]) begin
|
if (!instr_i[14]) begin
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr);
|
str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr);
|
||||||
end else begin
|
end else begin
|
||||||
str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, zimm_rs1_type, csr);
|
str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, zimm_rs1_type_i, csr);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endfunction // printCSRInstr
|
endfunction // printCSRInstr
|
||||||
|
|
@ -230,9 +230,9 @@ module ibex_tracer #(
|
||||||
logic [2:0] size;
|
logic [2:0] size;
|
||||||
begin
|
begin
|
||||||
// detect reg-reg load and find size
|
// detect reg-reg load and find size
|
||||||
size = instr[14:12];
|
size = instr_i[14:12];
|
||||||
if (instr[14:12] == 3'b111) begin
|
if (instr_i[14:12] == 3'b111) begin
|
||||||
size = instr[30:28];
|
size = instr_i[30:28];
|
||||||
end
|
end
|
||||||
|
|
||||||
case (size)
|
case (size)
|
||||||
|
|
@ -251,10 +251,10 @@ module ibex_tracer #(
|
||||||
|
|
||||||
regs_write.push_back('{rd, 'x});
|
regs_write.push_back('{rd, 'x});
|
||||||
|
|
||||||
if (instr[14:12] != 3'b111) begin
|
if (instr_i[14:12] != 3'b111) begin
|
||||||
// regular load
|
// regular load
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type), rs1);
|
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type_i), rs1);
|
||||||
end else begin
|
end else begin
|
||||||
printMnemonic("INVALID");
|
printMnemonic("INVALID");
|
||||||
end
|
end
|
||||||
|
|
@ -265,7 +265,7 @@ module ibex_tracer #(
|
||||||
string mnemonic;
|
string mnemonic;
|
||||||
begin
|
begin
|
||||||
|
|
||||||
case (instr[13:12])
|
case (instr_i[13:12])
|
||||||
2'b00: mnemonic = "sb";
|
2'b00: mnemonic = "sb";
|
||||||
2'b01: mnemonic = "sh";
|
2'b01: mnemonic = "sh";
|
||||||
2'b10: mnemonic = "sw";
|
2'b10: mnemonic = "sw";
|
||||||
|
|
@ -275,11 +275,11 @@ module ibex_tracer #(
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
if (!instr[14]) begin
|
if (!instr_i[14]) begin
|
||||||
// regular store
|
// regular store
|
||||||
regs_read.push_back('{rs2, rs2_value});
|
regs_read.push_back('{rs2, rs2_value_i});
|
||||||
regs_read.push_back('{rs1, rs1_value});
|
regs_read.push_back('{rs1, rs1_value_i});
|
||||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1);
|
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type_i), rs1);
|
||||||
end else begin
|
end else begin
|
||||||
printMnemonic("INVALID");
|
printMnemonic("INVALID");
|
||||||
end
|
end
|
||||||
|
|
@ -292,8 +292,8 @@ module ibex_tracer #(
|
||||||
mailbox #(instr_trace_t) instr_wb = new ();
|
mailbox #(instr_trace_t) instr_wb = new ();
|
||||||
|
|
||||||
// cycle counter
|
// cycle counter
|
||||||
always_ff @(posedge clk, negedge rst_n) begin
|
always_ff @(posedge clk_i, negedge rst_ni) begin
|
||||||
if (!rst_n) begin
|
if (!rst_ni) begin
|
||||||
cycles = 0;
|
cycles = 0;
|
||||||
end else begin
|
end else begin
|
||||||
cycles = cycles + 1;
|
cycles = cycles + 1;
|
||||||
|
|
@ -302,9 +302,9 @@ module ibex_tracer #(
|
||||||
|
|
||||||
// open/close output file for writing
|
// open/close output file for writing
|
||||||
initial begin
|
initial begin
|
||||||
wait(rst_n == 1'b1);
|
wait(rst_ni == 1'b1);
|
||||||
wait(fetch_enable == 1'b1);
|
wait(fetch_enable_i == 1'b1);
|
||||||
$sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id);
|
$sformat(fn, "trace_core_%h_%h.log", cluster_id_i, core_id_i);
|
||||||
$display("[TRACER] Output filename is: %s", fn);
|
$display("[TRACER] Output filename is: %s", fn);
|
||||||
f = $fopen(fn, "w");
|
f = $fopen(fn, "w");
|
||||||
$fwrite(f, " Time Cycles PC Instr Mnemonic\n");
|
$fwrite(f, " Time Cycles PC Instr Mnemonic\n");
|
||||||
|
|
@ -314,27 +314,27 @@ module ibex_tracer #(
|
||||||
$fclose(f);
|
$fclose(f);
|
||||||
end
|
end
|
||||||
|
|
||||||
assign rd = instr[`REG_D];
|
assign rd = instr_i[`REG_D];
|
||||||
assign rs1 = instr[`REG_S1];
|
assign rs1 = instr_i[`REG_S1];
|
||||||
assign rs2 = instr[`REG_S2];
|
assign rs2 = instr_i[`REG_S2];
|
||||||
assign rs3 = instr[`REG_S3];
|
assign rs3 = instr_i[`REG_S3];
|
||||||
|
|
||||||
// log execution
|
// log execution
|
||||||
always @(negedge clk) begin
|
always @(negedge clk_i) begin
|
||||||
instr_trace_t trace;
|
instr_trace_t trace;
|
||||||
mem_acc_t mem_acc;
|
mem_acc_t mem_acc;
|
||||||
// special case for WFI because we don't wait for unstalling there
|
// special case for WFI because we don't wait for unstalling there
|
||||||
if ( (id_valid || mret_insn || ecall_insn || pipe_flush || ebrk_insn || dret_insn ||
|
if ( (id_valid_i || mret_insn_i || ecall_insn_i || pipe_flush_i || ebrk_insn_i || dret_insn_i ||
|
||||||
csr_status || ex_data_req) && is_decoding) begin
|
csr_status_i || ex_data_req_i) && is_decoding_i) begin
|
||||||
trace = new ();
|
trace = new ();
|
||||||
|
|
||||||
trace.simtime = $time;
|
trace.simtime = $time;
|
||||||
trace.cycles = cycles;
|
trace.cycles = cycles;
|
||||||
trace.pc = pc;
|
trace.pc = pc_i;
|
||||||
trace.instr = instr;
|
trace.instr = instr_i;
|
||||||
|
|
||||||
// use casex instead of case inside due to ModelSim bug
|
// use casex instead of case inside due to ModelSim bug
|
||||||
casex (instr)
|
casex (instr_i)
|
||||||
// Aliases
|
// Aliases
|
||||||
32'h00_00_00_13: trace.printMnemonic("nop");
|
32'h00_00_00_13: trace.printMnemonic("nop");
|
||||||
// Regular opcodes
|
// Regular opcodes
|
||||||
|
|
@ -395,45 +395,45 @@ module ibex_tracer #(
|
||||||
{25'b?, {OPCODE_LOAD}}: trace.printLoadInstr();
|
{25'b?, {OPCODE_LOAD}}: trace.printLoadInstr();
|
||||||
{25'b?, {OPCODE_STORE}}: trace.printStoreInstr();
|
{25'b?, {OPCODE_STORE}}: trace.printStoreInstr();
|
||||||
default: trace.printMnemonic("INVALID");
|
default: trace.printMnemonic("INVALID");
|
||||||
endcase // unique case (instr)
|
endcase // unique case (instr_i)
|
||||||
|
|
||||||
// replace register written back
|
// replace register written back
|
||||||
foreach(trace.regs_write[i]) begin
|
foreach(trace.regs_write[i]) begin
|
||||||
if ((trace.regs_write[i].addr == ex_reg_addr) && ex_reg_we) begin
|
if ((trace.regs_write[i].addr == ex_reg_addr_i) && ex_reg_we_i) begin
|
||||||
trace.regs_write[i].value = ex_reg_wdata;
|
trace.regs_write[i].value = ex_reg_wdata_i;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// look for data accesses and log them
|
// look for data accesses and log them
|
||||||
if (ex_data_req) begin
|
if (ex_data_req_i) begin
|
||||||
|
|
||||||
if (!ex_data_gnt) begin
|
if (!ex_data_gnt_i) begin
|
||||||
//we wait until the the gnt comes
|
//we wait until the the gnt comes
|
||||||
do @(negedge clk);
|
do @(negedge clk_i);
|
||||||
while (!ex_data_gnt);
|
while (!ex_data_gnt_i);
|
||||||
end
|
end
|
||||||
|
|
||||||
mem_acc.addr = ex_data_addr;
|
mem_acc.addr = ex_data_addr_i;
|
||||||
mem_acc.we = ex_data_we;
|
mem_acc.we = ex_data_we_i;
|
||||||
|
|
||||||
if (mem_acc.we) begin
|
if (mem_acc.we) begin
|
||||||
mem_acc.wdata = ex_data_wdata;
|
mem_acc.wdata = ex_data_wdata_i;
|
||||||
end else begin
|
end else begin
|
||||||
mem_acc.wdata = 'x;
|
mem_acc.wdata = 'x;
|
||||||
end
|
end
|
||||||
//we wait until the the data instruction ends
|
//we wait until the the data instruction ends
|
||||||
do @(negedge clk);
|
do @(negedge clk_i);
|
||||||
while (!data_valid_lsu);
|
while (!data_valid_lsu_i);
|
||||||
|
|
||||||
if (!mem_acc.we) begin
|
if (!mem_acc.we) begin
|
||||||
//load operations
|
//load operations
|
||||||
foreach(trace.regs_write[i])
|
foreach(trace.regs_write[i])
|
||||||
trace.regs_write[i].value = lsu_reg_wdata;
|
trace.regs_write[i].value = lsu_reg_wdata_i;
|
||||||
end
|
end
|
||||||
trace.mem_access.push_back(mem_acc);
|
trace.mem_access.push_back(mem_acc);
|
||||||
end
|
end
|
||||||
trace.printInstrTrace();
|
trace.printInstrTrace();
|
||||||
end
|
end
|
||||||
end // always @ (posedge clk)
|
end // always @ (posedge clk_i)
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue