- Instruction addresses are now checked in the IF stage, after the cache
and after the prefetch buffer.
- To deal with unaligned instructions, the PMP logic checks the current
address and the next in parallel.
- The spec_branch timing hack has been removed as it's no longer
relevant with the PMP logic moved.
- Various updates made to the icache testbench to account for the
changes.
- Relates to #1471
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit amends some paths in the vendoring hjson file (and updates
config files to use things at the new paths). Finally it re-runs the
vendoring tool:
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
92e9242424c72c59008e267dd3779e2af5ec8e83
which just ends up with a load of file renames.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This now allows you to specify how many seeds to run. Sadly, you can't
say "give me 10 seeds, starting at 1234" because dvsim doesn't support
that at the moment. But it does at least avoid quite such long command
lines.
Instead of:
../../../../vendor/lowrisc_ip/dvsim/dvsim.py \
ibex_icache_sim_cfg.hjson \
--scratch-root ../../../../build \
--reseed 5 \
-c
you can run:
make RESEED=5 COVERAGE=1
One aspect of (i)cache design that I didn't know about before writing
test code for this block is the problem of multi-way hits. The icache,
as implemented, stores data to parallel ways and it's possible for a
fetch to match more than one way. The data from matching ways all gets
ORed together, which doesn't matter so long as it never
changes (because V | V == V for all V).
Of course, things go poorly if you have two different values, V and W,
at an address which are both stored in the cache. Then the result is V
| W, which isn't necessarily equal to either instruction.
Avoiding this needs priority encoders, which are rather large, so it
seems the usual approach is to disallow branching to modified code
before flushing the cache. This patch teaches the testbench to do this
properly.
Sadly, this means there's now a connection between the core agent and
the memory agent: the memory agent can no longer generate new seeds
whenever it pleases.
