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Author SHA1 Message Date
Hailin
1ac25b8089 [test] Performance evaluation 2023-03-31 15:58:32 +02:00
Hailin
13bbaf72d9 [test] Connect FPU subsystem 2023-03-31 15:58:32 +02:00
Pirmin Vogel
83588ae089 [vendor] Vendor in FPU subsystem and dependencies 
This commit vendors in the FPU subsystem from the PULP project as well
as its dependencies such as:
- CVFPU from OpenHW Group (formerly FPnew from the PULP project)
- FPU DIV SQRT MVP from the PULP project
- common cells from the PULP project

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2023-03-31 15:58:32 +02:00
Hailin
cfa51bebcf [rtl] Performance Counters 
Add performance counters for CV-XIF
 2023-03-31 15:29:50 +02:00
Hailin
129af7a53b [rtl] Add memory and memory result interfaces 
This commit adds memory interface and memory result interface
of the RISC-V Extension Interface.
 2023-03-31 15:29:50 +02:00
Hailin
8ad0d7c9d4 [rtl] Add issue, commit, and result interfaces 
This commit adds issue interface, commit interface,
and result interface of the RISC-V Extension Interface.
 2022-10-04 12:10:51 +02:00
Hailin
36ea2210de [rtl] Change parameter type 
This commit changes parameter type from 'int' to 'unsigned int'
according to CV-XIF standard update.
 2022-06-22 16:37:05 +02:00
Hailin
d533faf086 [rtl] Add compressed interface 
This commit adds compressed interface of the RISC-V Extension Interface.
This commit have passed verification with pseudo compressed accelerator.
 2022-05-05 13:50:02 +02:00
Rupert Swarbrick
0a9f5ed1da [rtl] Remove "mispredict" ports from icache 
These are no longer needed: a previous commit has moved the logic that
handles misprediction into the IF stage and branch_mispredict_i was
dead zero.
 2022-04-04 16:56:04 +01:00
Rupert Swarbrick
618f1f08bd [rtl] Remove "mispredict" ports from prefetch buffer 
These are no longer needed: a previous commit has moved the logic that
handles misprediction into the IF stage and branch_mispredict_i was
dead zero.
 2022-04-04 16:56:04 +01:00
Rupert Swarbrick
59a4d11c10 [rtl] Combine the two branch signals in the IF stage 
The prefetch buffer and icache both treat the branch_i and
branch_mispredict_i signals identically, so it's a bit cleaner to pull
that treatment up into ibex_if_stage.sv

This commit doesn't change the modules below: it just passes zeros for
the "mispredict" version. Removing those ports will be done in a
follow-up commit.
 2022-04-04 16:56:04 +01:00
Canberk Topal
a3e5eebffa [dv,fcov] Timeout fix + removing .ccf from yaml 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-04-04 15:33:14 +01:00
Canberk Topal
9acd2583e1 Update google_riscv-dv to google/riscv-dv@6e0dc18 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6e0dc183a4678bfd581c1021b5ab7705f31d14a5

* [XCelium] Enable coverage collection with XCelium (Canberk Topal)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-04-04 15:33:14 +01:00
Canberk Topal
d659c96cda Update lowrisc_ip to lowRISC/opentitan@3a33c4df2 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
3a33c4df2ed31b0d7a8936531a4ae9a275177f1b

* [prim,rtl] Pass addr_i in no scrambling case (Canberk Topal)
* [dvsim,xcelium] Avoid an OPTP2ND error if a plusarg isn't set
  (Rupert Swarbrick)
* [dv,tcl] Merge Coverage Databases with union_all (Canberk Topal)
* [prim_count] Add missing include (Pirmin Vogel)
* [sram_ctrl] Additional write gating based on intg error (Michael
  Schaffner)
* [sram_ctrl] Remove nonce reversal to improve timing (Michael
  Schaffner)
* [sram_ctrl] Retime address mux to improve timing (Michael Schaffner)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-04-04 15:33:14 +01:00
Greg Chadwick
a3b50fb694 [doc, fcov] Remove coverpoint names from unimplemented coverage 2022-04-04 13:05:55 +01:00
Greg Chadwick
fbf4b6a5b2 [doc, fcov] Tweak and add coverpoints 
Moved some from 'Miscellaneous' to 'Exceptions/Interrupts/Debug' and
added some details along with a couple of new coverpoints.
 2022-04-04 13:05:55 +01:00
Greg Chadwick
ead2174c1a Introduce internal interrupt concept 
An internal interrupt triggers an NMI. A single one is implemented, one
on integrity errors being seen in load data. This replaces a synchronous
exception on an integrity error which caused timing issues.
 2022-04-01 17:00:23 +01:00
Canberk Topal
4a2427cd32 Fix cov_report directory in sim.py 
Enables us to save coverage groups text file which helps easily see the overall
coverage in a regression.
 2022-04-01 15:46:32 +01:00
Pirmin Vogel
db926e5ef5 [ram_2p] Set DataBitsPerMask parameter for prim_ram_2p 
It turned out that with the default value of 1, Vivado infers a separate
18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA
examples. This can be very wasteful in terms of resource utilization
especially for smaller configurations.

As our examples don't use ECC or parity and mainly target simualation
and FPGA, it's better to use a value of 8 for the DataBitsPerMask
parameter. Vivado will then not distribute words across different BRAM
instances which results in more efficient FPGA resource utilization.

For a detailed analysis and explanation, please refer to
lowRISC/Ibex#1587.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-04-01 16:32:45 +02:00
Pirmin Vogel
fe3e029108 Update google_riscv-dv to google/riscv-dv@cb4295f 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cb4295f9ce5da2881d7746015a6105adb8f09071

* Update list search (Matthew Ballance)
* Trap and report exceptions encountered in sub-processes and
  propagate error back (Matthew Ballance)
* Workaround fix for loop test colon issue (aneels3)
* Fix typo (aneels3)
* Add support for RV64AFD (aneels3)
* Fix typo (aneels3)
* Update README.md (aneels3)
* Add support for sub_programs (aneels3)
* fix issue with imm value for 64 bit instr (aneels3)
* Allow for underscores and capital letters in ISA for ISS (Pirmin
  Vogel)
* implement rv64i (shrujal20)
* Add support for RV32FD coverage (aneels3)
* Integrate random seed for pyflow (aneels3)
* Add riscv_loop_test (ShraddhaDevaiya)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-04-01 16:15:35 +02:00
Canberk Topal
2fc4cde7d2 [dv,xlm] Pass simulator flag to cov.py in Makefile 
Enables us to work with only xlm licences when doing the coverage.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-03-31 15:36:06 +01:00
Canberk Topal
4c1a4ed1df Update lowrisc_ip to lowRISC/opentitan@0747afbdd 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
0747afbddec0ad176980429fe3100b32edb71d4a

* [dv] Enable C/C++ code sourcing with VCS in .core (Canberk Topal)
* [dv/dv_base_reg] Remove duplicated `get_map_by_name` method (Cindy
  Chen)
* [prim] Pulse Sync assertion to check input/output (Eunchan Kim)
* [sparse_fsm_flop] Create flop macro to increase DV coverage (Michael
  Schaffner)
* [dvsim] Make build-randomization opt-in (Srikrishna Iyer)
* [xcelium] Fix compile error (Srikrishna Iyer)
* [dv/cov] fpv_csr_assert only collect assertion coverage (Cindy Chen)
* [dv/jtag] Fix chip_level jtag csr rw failure (Cindy Chen)
* [rtl] Convert some non-ANSI parameters to localparams (Rupert
  Swarbrick)
* [prim] Waive unused parameters for Verilator in prim_generic_otp
  (Rupert Swarbrick)
* [prim] Make a variable widening explicit in prim_present.sv (Rupert
  Swarbrick)
* [prim] Waive some ALWCOMBORDER Verilator warnings in prim_arbiter_*
  (Rupert Swarbrick)
* [prim] Fix Verilator lint warnings in prim_gf_mult.sv (Rupert
  Swarbrick)
* [prim] Make some widening comparisons explicit in prim_clock_*.sv
  (Rupert Swarbrick)
* [prim] Waive unused EnableAlertTriggerSVA for verilator lint (Rupert
  Swarbrick)
* [bazel,dvsim] Add build rules for dvsim.py (Timothy Trippel)
* [prim] Fix a bunch of Verilator lint errors in prim_packer.sv
  (Rupert Swarbrick)
* [prim_sparse_fsm_flop/lint] Move waiver to correct file (Michael
  Schaffner)
* [rv_dm dv] Test drive compile-time seed (Srikrishna Iyer)
* [dvsim] Introduce Verilog compile-time seeds (Srikrishna Iyer)
* [dvsim] Treat `tests: ["N/A"]` as an ignored testpoint (Srikrishna
  Iyer)
* [hw/dv] Removed colon from Questa build and run fail patterns.
  (David Pudner)
* [hw/dv] Code review changes for running questa simulations. (David
  Pudner)
* [hw/dv] Added apache license header to questa_initial_setup.sh.
  (David Pudner)
* [doc/ug] Updated opentitan documentation to include information
  about Questa use. (David Pudner)
* [hw/dv] Added Questa dvsim files (David Pudner)
* [dv/unr] Blackbox common security modules from UNR flow (Cindy Chen)
* [dv] Minor fix to error message in mem_model.sv (Rupert Swarbrick)
* [keymgr] Update keymgr to use prim_edn_req (Timothy Chen)
* [doc] Fix rendering of special characters in testplan table (Rupert
  Swarbrick)
* [dv] enable tlul_assert for csr part2 (Rasmus Madsen)
* [dv] Enable tlul_assert for CSR tests (Weicai Yang)
* [dv] Add valid/ready req/ack coverage for push_pull agent (Weicai
  Yang)
* [dv,verilator] Make multiple sim_ctrl extensions play nicely (Rupert
  Swarbrick)
* [chip dv] Add AST initialization routine (Srikrishna Iyer)
* [top] auto generate (Timothy Chen)
* [reggen] Make field 'qe' behavior consistent (Timothy Chen)
* [prim] IFDEF_CODE waiver in sparsefsm flop (Eunchan Kim)
* [dv] Update checklist for all blocks (Weicai Yang)
* [dv/entropy_src] Temp remove stress_all_with_rand_reset test (Cindy
  Chen)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-03-31 15:20:56 +01:00
Canberk Topal
68b56ef0f5 Include the main C++ file only with Verilator 
This is necessary for having VCS support with simple system example.
Because in the ibex_simple_system_main.cc we are including some
Verilator exclusive header files.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-03-31 14:26:29 +01:00
Canberk Topal
db0b89a7ed [dv,xlm] Save each UCM file in <test_name>.<seed> 
This enables to have a coverage report in instances where we have
different types of tests.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-03-31 14:11:12 +01:00
Canberk Topal
6884f6b990 Coverage support with Cadence Tools 
Enables coverage collection while running the ibex-dv with xcelium.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-03-30 17:11:17 +01:00
Prajwala Puttappa
2317bb7fc0 [icache, dv] Added ram interface and enables ecc error injection. 
This commit adds ibex_icache_ram_if to connect between DUT and tag /
data RAMs.

This interface injects 1 or 2 bit error on rdata if enable_ecc_errors
bit is set. It also checks that ecc_err_o pin is asserted by DUT
whenever an ecc error is injected.

ibex_icache_ecc_vseq and ibex_icache_base_vseq have been modified to
inject ecc errors through the ram interface.
 2022-03-29 16:06:44 +01:00
Prajwala Puttappa
eea478be51 [icache, dv] Removed ecc agent 
This commit removes ecc agent from the testbench. Following PRs will add
changes to drive the rdata pin (input to icache) with 1 or 2 bits
flipped.
 2022-03-29 16:06:44 +01:00
Harry Callahan
98931c7dff Remove logfile param in Ibex RTL Sim for Xcelium 
Fixes a bug where both Xcelium and Python open the same sim.log file and race to
write the simulation results into it. This change makes Python the sole writer of this
file using the captured stdout/stderr from the subprocess.run call in
run_rtl.py.

This bug was also previously present for VCS but was fixed in 90ff7ca6c.
 2022-03-28 17:50:22 +01:00
Greg Chadwick
72acfe2fca [fcov, doc] Update coverage plan 
Added coverpoint and cross names to relevant plan entries so plan is up
to date with implemented coverage. Also some minor changes to remove
plan entries that are no longer required.
 2022-03-28 14:53:27 +01:00
Greg Chadwick
aee235cfa6 [fcov] Add and improve functional coverage 2022-03-28 14:53:27 +01:00
Greg Chadwick
d88e5f8ce4 [rtl] Refactor pmp logic 2022-03-28 14:53:27 +01:00
Greg Chadwick
90918dff1d [rtl] Refactor illegal instruction logic 
This groups the various different illegal instructions categories within
ibex_id_stage rather than spreading them between ibex_id_stage and
ibex_controller.
 2022-03-28 14:53:27 +01:00
Greg Chadwick
9fd512bdbd [rtl] Refactor illegal debug CSR logic 2022-03-28 14:53:27 +01:00
Greg Chadwick
36d77ab0c5 [ci] Fix coremark cosim job 
Actually fail the job if there's an error
 2022-03-22 16:29:03 +00:00
Greg Chadwick
7508644c6e [simple_system_cosim] Switch to latest cosim version 2022-03-22 16:29:03 +00:00
Greg Chadwick
93b71e2190 [simple_system] Fix GetIsaString 
Spike expects extension letters to be in a particular order
 2022-03-22 16:29:03 +00:00
Greg Chadwick
4fa6329c58 [cosim] Fix cosim mcycle update 
This resolves an off by one issue
 2022-03-22 16:29:03 +00:00
Greg Chadwick
f44ae90040 [doc] Update coverage plan 2022-03-21 14:52:26 +00:00
Prajwala Puttappa
07a49045fb [ibex, dv] Removed extra hierarchy of ic_top inside icache TB 
This commit removes extra hierarchy of ic_top inside icache TB and moves
the scrambling request generation logic and instantiation of data and
tag RAMs to tb.
 2022-03-18 18:32:20 +00:00
Rupert Swarbrick
96d8aa6c15 Update spike_cosim.cc to be able to build against newer Spikes 
This should work with versions ibex-cosim-v0.1 and ibex-cosim-v0.2.
 2022-03-18 15:24:46 +00:00
Rupert Swarbrick
63509ff4da [dv,core_ibex] Fix order of 'm' and 'c' in ISA string 
Recent versions of Spike allow rv32imc but not rv32icm.
 2022-03-18 15:24:37 +00:00
Prajwala Puttappa
6bb67e20f8 [icache, dv] Added scrambling agent to verify scrambling in RAMs 
This commit adds a new scrambling agent to drive scrambling key and
valid to the data and tag memory interfaces.

Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5

Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
 2022-03-18 10:33:27 +00:00
Prajwala Puttappa
9ef123f2b1 [icache, dv] Removed support for single clock cycle PMP error response 
Earlier the design supported single clock cycle error responses from PMP
block whenever a read was done from blocked memory. Now there is at
least one clock cycle delay after the request has been granted for the
error to be asserted. Therefore, this commit removes the support for
single clock cycle PMP error response.
 2022-03-17 18:07:16 +00:00
Prajwala Puttappa
c900ef1476 Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5

Please note that we're adding push_pull_agent for the first time in this
commit.

Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
 2022-03-17 18:06:56 +00:00
Prajwala Puttappa
be5fffa656 [icache, dv] Fixed regression failure in ibex_icache_back_line 
There was issue with rtespect to calculating number of instructions per
word and this commit fixes that issue.

Number of instructions per word = 1/4*1 + 3/4(1/4*3/2 + 3/4*2) = 53/32.
Earlier th5s was calculated as 7/4.
Ideal window length needed to calculate fetch ratio percentage is
calculated as 53/32*C*2 = 848. Earlier it was calculated to be 300.
 2022-03-17 14:57:53 +00:00
Greg Chadwick
f7724adcc7 [rtl] Move memory ECC checks and generation into core 
Previously integrity checks for incoming memory reads and integrity
generation for outgoing memory writes were handled within ibex_lockstep
and weren't duplicated.

This moves the integrity checks and generation into the core so they are
replicated and checked as part of the lockstep mechanism.

Additionally it generates a bus error on any memory integrity check
failure. This will result in Ibex taking an exception if any data read
or instruction fetch has bad integrity.
 2022-03-16 10:21:03 +00:00
Rupert Swarbrick
2f1e188346 Fix port list in top_artya7 example 
The "alert_major" port was split into "internal" and "bus" parts back
in commit 9943f9a. Update the example to match.
 2022-03-15 15:37:03 +00:00
Greg Chadwick
094451a948 [doc] Add examples info to README 2022-03-11 17:28:52 +00:00
Prajwala Puttappa
0a8b4a4f61 [icache, dv] Made changes required to make TB compatible with Xcelium 2022-03-10 14:18:50 +00:00
Prajwala Puttappa
15da12dfd6 Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5

* Revert "[dv] Allow using memutil_dpi_scrambled even without
  prim_ram_1p_scr" (Rupert Swarbrick)
* [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick)
* [dv] Make an implicit up-conversion explicit (Rupert Swarbrick)
* [dv] Remove an unused array variable in prince_ref.h (Rupert
  Swarbrick)
* [prim/security] Improve the code for prim_sparse_fsm security check
  (Cindy Chen)
* [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off
  (Weicai Yang)
* [all] variety of minor lint fixes (Timothy Chen)
* [dv] Add options to improve VCS runtime (Weicai Yang)
* [rv_dm] CSR test fixes (Srikrishna Iyer)
* [dvsim] Fix pass/fail status for synthesis regression (Michael
  Schaffner)
* [prim] Minor lint fixes for unused clocks / resets (Timothy Chen)
* [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner)
* [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen)
* [rstmgr] Address several d2s review items (Timothy Chen)
* [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen)
* [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer)
* [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer)
* [dv] Print computed CSR stuff in RAL (Srikrishna Iyer)
* [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer)
* [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy
  Chen)
* [prim] Add prim_and2 primitive (Pirmin Vogel)
* [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel)
* [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives
  (Pirmin Vogel)
* [prim_dom_and_2share] Switch to single randomness input (Pirmin
  Vogel)
* [util/dvsim] Fix confusing error message (Guillermo Maturana)
* [dvsim] Minor changes to SynCfg results reporting (Michael
  Schaffner)
* [fpv] V2S formal support (Cindy Chen)
* [tools/xcelium] updated common coverage exclusions to exclude single
  bit correctly (Rasmus Madsen)
* [dv] Clean up enable_reg_testplan (Weicai Yang)
* [top] Hook-up flash/otp control and observation bus to ast (Timothy
  Chen)
* [lint] Increase the unroll count (Eunchan Kim)
* [entropy_src] Document & Implement THRESHOLD_SCOPE (Martin Lueker-
  Boden)
* [AST] USB Observe, Clocks & POR_NI logic update (Jacob Levy)
* [prim] Add new assertion macro for generating static lint errors
  (Pirmin Vogel)
* [dv] csr_seq_lib fixes (Srikrishna Iyer)
* [dv] dv_base_reg_block - Add special knobs (Srikrishna Iyer)
* [dv] dv_base_mem - add special knobs (Srikrishna Iyer)
* [prim] Move sec_cm assertion to an include file in prim_assert
  (Weicai Yang)
* [flash_ctrl] Fixes for erase suspend (Timothy Chen)
* [dv] exclude d_user.rsp_intg[6] for xcelium (Weicai Yang)
* [prim_flop_en] Dependency fix (Michael Schaffner)
* [dv] add mubi coverage for CSR and update reggen (Weicai Yang)
* [prim] Add option for secure buffers in prim_mubi (Timothy Chen)
* [prim] Add option for hand instantiated buffers for prim_flop_en
  (Timothy Chen)
* [dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen)
* [prim_count] Updated comments to reflect all changes in
  lowRISC/opentitan#10378 (Michael Tempelmeier)
* [dv] Teach ECC32 flavours of mem_area to write with integrity bits
  (Rupert Swarbrick)
* [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen)
* [checklists] Update V2S checklists (Srikrishna Iyer)
* [tools/xcelium] updated xcelium flow to vcs for coverage test
  grading (Rasmus Madsen)
* [prim] Add stub flops to remove lint warnings (Timothy Chen)
* [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang)
* [dvsim] Add support for tags in testplan (Srikrishna Iyer)
* [dv] Enable xcelium to include X for toggle coverage (Weicai Yang)
* [dv] Clean up mem_bkdr_util__sram (Weicai Yang)
* [util, testplan] Allow relative testplan imports (Srikrishna Iyer)
* [prim] Add phase output to shadow register primitive (Pirmin Vogel)
* [dv] Add assertion to check double_lfsr err triggers an alert
  (Weicai Yang)
* [dv] Fix foundary failure (Weicai Yang)
* [prim] update prim_count comment (Timothy Chen)
* [prim_flop_2sync] Make the prim a standard non-generated prim
  (Michael Schaffner)
* [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen)
* [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy
  Chen)
* [dv] Add countermeasure verification for double_lfsr (Weicai Yang)
* [dv] Update countermeasure verification (Weicai Yang)
* [doc] Update V2S items (Weicai Yang)
* [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded
  (Michael Schaffner)
* [prim_max_tree/fpv] Add a simple formal testbench (Michael
  Schaffner)
* [prim_max_tree] Create a primitive that calculates maxima (Michael
  Schaffner)
* [dv] CSR / RAL model fixes (Srikrishna Iyer)
* [uvmdvgen] bug fix (Srikrishna Iyer)
* [dv] Fix some Xcelium warnings (Srikrishna Iyer)
* [dv] Disable some benign warnings (Srikrishna Iyer)
* [prim_mubi*_sender] Add option to omit sender flops (Michael
  Schaffner)
* [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer)
* [keymgr] sparsify the data control fsm (Timothy Chen)
* [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner)
* [prim] Update behavior of prim_count (Timothy Chen)
* [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen)
* [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana)
* [sw,tests] SRAM execution test DV integration (Dave Williams)
* [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai
  Yang)
* [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala
  Puttappa)
* [rom_ctrl, dv] Fixes regression failures in
  rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa)
* [dv/chip] Add jtag_csr_rw seq (Cindy Chen)
* [chip dv] Remove xcelium build opt (Srikrishna Iyer)
* [doc] Reorder D2S checklist items (Michael Schaffner)
* [reggen] Add support for validation of RTL CM annotation (Michael
  Schaffner)
* [all] various simple lint fixes (Timothy Chen)
* [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert
  Swarbrick)
* [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen)
* [clkmgr] various spec and parameter updates (Timothy Chen)
* [dv] Add ASSERT_NET to check net value (Weicai Yang)
* [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934
  (Weicai Yang)
* [primgen] Update AscentLint waiver in generated abstract prim
  wrappers (Pirmin Vogel)
* [prim_generic] Fix lint errors (Pirmin Vogel)
* [prim_count] Fix lint warnings (Pirmin Vogel)
* [prim_alert_receiver] Fix ping during init sequence bug (Michael
  Schaffner)
* [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa)
* [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer)
* [prim_filter_cnt] Make threshold runtime programmable (Michael
  Schaffner)
* [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter*
  (Michael Schaffner)
* [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to
  V2S (Weicai Yang)
* [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel)
* [sram/dv] Enable the integrity test for passthru (Weicai Yang)
* [dv] Add integrity test for passthru mem (Weicai Yang)
* [dv/tools] Fix alert ping exclusion (Cindy Chen)
* [dv/mem_bkdr_util] added backdoor write of LC counter into LC
  partition in OTP (Dror Kabely)
* [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner)
* [prim_clock_mux] Model generic mux with boolean ops (Michael
  Schaffner)
* [prim_buf] Ensure generic primitives contain a logic cell (Michael
  Schaffner)
* [prim_count] improved documentation and style (Michael Tempelmeier)
* Revert "[dv] Replace fileset_partner flag with fileset_ast flag"
  (Michael Schaffner)
* [dv] Replace fileset_partner flag with fileset_ast flag (Sharon
  Topaz)
* [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang)
* [dv/prim_alert] Add V3 item to testplan (Cindy Chen)
* [dv/prim_count] Add an assertion to check max count stable (Cindy
  Chen)
* [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick)
* [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ
  (Rupert Swarbrick)
* [doc/checklist] Template fix (Cindy Chen)
* [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert
  Swarbrick)
* [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC
  codes (Michael Schaffner)
* [dv/prim_alert_tb] Modify the seq to ensure alert always sends
  (Cindy Chen)
* [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error.
  (Timothy Trippel)
* [dv/prim_alert] Add randomization in ping request sequence (Cindy
  Chen)
* [prim_alert_receiver] Only check for ping requests after
  initialization (Michael Schaffner)
* [doc] Update D2S checklist template and description (Michael
  Schaffner)
* [prim_esc_receiver] Switch to standardized prim_count (Michael
  Schaffner)
* [prim_count] Add option to disable the connection SVA (Michael
  Schaffner)
* [otbn, rtl] Lint fixes (Greg Chadwick)
* [sram/dv] Better support partial write in scb (Weicai Yang)
* [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy
  Chen)
* [secded/lint] Fix lint errors (Michael Schaffner)
* [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen)
* [alert_handler] Switch to sparse fsm primitive (Michael Schaffner)
* [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael
  Schaffner)

Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
 2022-03-10 14:15:03 +00:00