Commit graph

61 commits

Author SHA1 Message Date
Tom Roberts
2aacd2b98b [Priv modes] Add support for U-Mode
- General changes to suport U-mode (fixes #88)
- Update documentation
- Add priv mode flops to CSRs module
- Propagate correct priv mode to PMP module
- Implement CSR priv-mode permission checking
- Implement illegal U-mode instruction checking
- Add extra mstatus bits for U-mode (MPRV and TW)
2019-10-03 10:41:29 +01:00
Tom Roberts
892ad8a621 [RTL] - Add PMP module
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
  I-side and LSU
- Each of those units progresses with their request as-if it was granted
  externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
  an exception
2019-08-29 17:43:37 +01:00
Philipp Wagner
7eee24c094 Mention CREDITS.md in license header 2019-08-27 18:10:02 +01:00
Philipp Wagner
14b8f88957 Replace author credits in files with CREDITS.md
We currently have a documentation block at the beginning of each file,
containing author credits and module-level documentation. The
module-level documentation is retained for historic reasons and
duplicated with the newer comments below it.

For the authors, maintaining author credits in the file is error-prone,
as this information gets outdated very soon. A more reliable way to see
who modified a file is to use the history information in git.
Additionally, we now have the CREDITS.md file, which lists all
contributors, even the ones which don't appear in the git history (e.g.
because the code was copied and commited by someone else).
2019-08-27 18:10:02 +01:00
Tom Roberts
44b033cf8b [rtl] Add support for instruction fetch errors
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
Pirmin Vogel
964e62afee CSRs: remove `define for mstatus CSR handling 2019-07-29 15:55:48 +01:00
Pirmin Vogel
6d72aebc16 Correct cause number for illegal instruction exception
This bug has beed reported by @taoliug. This resolves #195.
2019-07-26 11:38:09 +01:00
Pirmin Vogel
327d836281 Add non-maskeable interrupt (NMI) 2019-07-24 14:22:00 +01:00
Pirmin Vogel
71a33e1ca1 Add local fast interrupts, remove legacy interrupts
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
2019-07-24 14:22:00 +01:00
Pirmin Vogel
c2fffe0440 Add mip and mie CSRs + interrupts
This commit adds the `mip` and `mie` CSRs as well as the software,
timer and external interrupts.

Currently these interrupts are overlapped with some of the legacy
interrupts, i.e., the core will jump to the same address for different
interrupts. For example, the software interrupt has the same ID as
legacy interrupt #3. Thus, the handler must read the `mip` register
to find out whether the interrupt routine has been entered because of
the software interrupt or the legacy interrupt.

Eventually, the number of legacy interrupts will be reduced to avoid
this overlapping, and they will be connected to the `mie` and `mip`
CSRs directly.
2019-07-24 14:22:00 +01:00
Philipp Wagner
428d057c4a Rename ibex_[tracer_]define to ibex_[tracer_]pkg
This file doesn't contain defines any more, but a normal SV package.

The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.

Fixes lowrisc/ibex#173
2019-07-19 11:34:40 +01:00
Renamed from rtl/ibex_defines.sv (Browse further)