Correcting some small issues that cause newer versions of OpenSTA to
fail (previously it issued an error and continued).
- ABC/OpenSTA disagree how set_driving_cell command works so introduce
seperate ABC SDC file
- Run clean before generating STA netlist, otherwise yosys generates
some assignements to unused wires that OpenSTA's verilog parser dislikes
Adds an 'uprate' clock period which is subtracted off the desired period
and given to ABC as the target clock period. This gives better overal
timing results with minimal area impact.
Adds significant functionality to synthesis flow. Timing reports are
generated using OpenSTA and an area report is generated. Flow supports
open Nangate45 library from OpenROAD.
