PAC instruction writes to the register file twice,
so when not taking stall_pa into consideration,
instr_id_done_o is activated twice during the execution of an PAC.
Unfortunately it interferes with the implementation of counters and
tracers for PAC, so now we are using stall_pa to calculate instr_id_done_o.
With the writeback stage enabled we execute the PAC/AUT instruction
before the required data is written to the register file.
For example, when the load instruction precedes AUT instruction,
AUT instruction is started before the loaded data is written
to the register file. It is a problem that the hazard detection
(stall_ld_hz) using rf_ren_a/b_o was not active for PAC/AUT instruction.
Also, I change codes not to activate pa_pac_en or pa_aut_en
when load hazard occurs.
- Add SECDED ECC checking to the register file when SecureIbex is
enabled
- No correction is attempted, but an alert is raised for the system to
intervene
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
But if you are using precompiled UVM it may be compiled with other timescale depending on compilation option used when it was compiled or tools default timescale value (uvm does not set timescale int the code).
In this case for us precompiled UVM timescale is 1ps/1ps - so UVM gets 1000000000 in set timeout but interprets it as ps. As a result timeout is 1000 times smaller that you expect. That is why we are getting timeouts.
It is hard to find perfect solution. One of them is to recompile the UVM with -timescale 1ns/ps (or whatever you will use for your design).
Fix a lint error reported by AscentLint:
```
E ALWAYS_SPEC: ibex_counter.sv:59 Edge triggered block may be more accurately modeled as always_ff New
```
* Mention the need to install `libelf-dev`. Thanks to Bert Pieters for
reporting this.
* Guide users to install our Python dependencies, including fusesoc and
edalize, from `python-requirements.txt`, to ensure they have the
right version.
* Prefer ELF files for Verilator simulations. This makes it easier to
use existing ELF files from another software build system.
Fixes#1019
We previously had a dependency on all primitives in Ibex, even though we
only depend on the LFSR primitive. Now that there's a more fine-grained
dependency available, we can use that.
This has the great benefit of restricting all lint tools to only the
code we're interested in, and not linting all primitives in OpenTitan
together with Ibex. This also helps tools like yosys, which aren't able
to parse all of OpenTitan's code yet.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ebf4663b42a9d81d026db5821b5c8249d54f23a7
* [prim_lfsr] Fix description in core file for FPV (Philipp Wagner)
* [prim_lfsr] Factor out into a separate core file (Philipp Wagner)
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
As a result of lowRISC/opentitan#2405 and lowRISC/ibex#928 (reporting
that interrupts that came in while a load instruction was in the ID
stage caused some incorrect behavior in Ibex), this PR adds some new
directed interrupt and debug tests to check that the core behaves
properly during execution of each supported instruction when some
external irq/debug stimulus comes in.
To do this, we use the two new functions `decode_instr(...)` and
`decode_compressed_instr(...)` in `core_ibex_test_list.sv` to "decode"
every instruction that the `core_ibex_instr_monitor_if` sees in the ID
stage of the pipeline. Once the testbench decodes an instruction that
we have not seen before, it can then drive interrupt or debug stimulus
into the core.
Once any given instruction has been detected by the testbench (and
stimulus driven), it will no longer drive stimulus if this instruction
is seen in the decode pipeline (e.g. if we have previously detected a
`c.addi` instruction in the ID stage and have driven irq/debug stimulus,
we will no longer drive stimulus if we see another `c.addi` instruction,
no matter the operands). This is to avoid driving irq/debug stimulus
after every single instruction as this will add a huge unwanted amount
of simulation latency.
A few notes:
- We drive irq/debug stimulus into the core every time we see a
`wfi` instruction, as otherwise we will timeout as the core waits
infinitely for some stimulus from the outside world.
- We ignore some system-level instructions (ebreak/mret/dret) and
illegal instructionsfor now, as driving stimulus during these
instructions will result in a nested trap, which requires special
handling.
- The interrupt agent was modified slightly to drive stimulus by
default on the falling edge of the clock, so this way we can "catch"
instructions that are in the ID pipeline for only a single cycle.
- The duration for which the testbench raises `debug_req_i` for the core
is also increased to avoid edge cases where we lower the debug line
too early (e.g. while long multicycle instructions like `div` are
executing in the ID stage).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
9ac4f9c8b924b79eb7d3581b29346a612f705751
* Allow verilated top-levels to do work after a simulation completes
(Rupert Swarbrick)
* Add some missing dependencies on lowrisc:prim:assert (Rupert
Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Use Xilinx-specific implementations for primitives, such as RAM and the
clock gate (which will now be implemented using a BUFGCE macro, and no
longer with a latch).
Verified in Vivado synthesis to pick up the Xilinx primitive now.
Support for this extension is not experimental (it's fully verified using
RISCV-DV) but the extension might change before being ratified.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- The "PINCONNECTEMPTY" waiver is part of our normal waiver file, no need
to add it to the tool invocation.
- Recent versions of Verilator choose good defaults for MAKE_OPTS,
passing it explicitly overrides the settings.
- All Verilator code is now lint clean, we can remove `-Wno-fatal`.
- FST traces are not much slower then VCD traces any more in recent
Verilator versions, remove the respective comment.
- Align comment about the compile/sim time for tracing with other files
and OpenTitan.
The clock gating primitive is now a dependency of the
lowrisc:ibex:ibex_core file directly and only used in there, we can
remove it from the simulation or FPGA dependency collections.
The only core which needs lint waivers is ibex_core.core; it will then
inherit those waivers to other cores, such as ibex_core_tracing.core,
and higher-up users of these cores (such as the simple system).
Also remove the Verible lint configuration, which happens to be the
default by now. This fixes#736 by making it unnecessary.
The lint target in ibex_core_tracing was used to also lint unrelated
files which are needed for some simulations (e.g. the simple system).
Remove them from there, as they really don't belong there.
Ibex depends on a clock gating primitive. This has always been the case;
previously, we have under-specified the dependency list by simply not
including this dependency. This is problematic not only because "IT'S
WRONG!", but also because it breaks self-contained targets, like
Verilator lint, which cannot run on ibex_core or ibex_core_tracing
without having a way to find the clock gating primitive.
Before we changed to vendoring in our RAM primitives from OpenTitan,
there was an SRAM_INIT_FILE define that you could stick in your core
file. That's now gone away, replaced by a parameter (MemInitFile). If
we want to plumb that in, we need to pass it properly through the
wrappers.
